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Ar ï¿½ï¿½ï¿½ï¿½ ï¿½ï¿½ï¿½ ï¿½ï¿½ ï¿½ï¿½ ï¿½ ï¿½&ï¿½ ï¿½ï¿½ï¿½R ï¿½ ï¿½ï¿½ G ï¿½ï¿½ï¿½ï¿½P9ï¿½ï¿½ ï¿½ï¿½ ï¿½i ï¿½ï¿½ï¿½ï¿½HJkï¿½ï¿½ï¿½Qeï¿½[ï¿½ï¿½ï¿½~Rï¿½Y ï¿½ï¿½ ï¿½Hï¿½3-ï¿½ï¿½aï¿½ï¿½ï¿½a6ï¿½ï¿½ï¿½ï¿½ ^ rp ï¿½I ï¿½ï¿½ ï¿½ï¿½.ï¿½ï¿½ ï¿½ï¿½ï¿½ï¿½Kï¿½ï¿½n ï¿½ï¿½ï¿½ï¿½ï¿½ ï¿½z ï¿½ï¿½xï¿½ ï¿½'[ O 2F ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ (P< ï¿½@ï¿½ï¿½ï¿½ï¿½ï¿½w0ï¿½ 6%ï¿½qY 2ï¿½ï¿½ï¿½ï¿½1?ï¿½s ï¿½ ï¿½BBï¿½9nV7rï¿½ï¿½ï¿½I^ï¿½} ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½Lï¿½D ï¿½kï¿½ ï¿½ï¿½ï¿½Mï¿½ï¿½ï¿½ï¿½Vï¿½Gt.ï¿½W6ï¿½ï¿½ *ï¿½sï¿½j= `ï¿½HMBï¿½ï¿½ï¿½ï¿½ï¿½- ï¿½ï¿½ ï¿½ï¿½bï¿½ï¿½tï¿½Hw ï¿½ï¿½ ï¿½ï¿½ï¿½ï¿½ï¿½ K je lï¿½%=0 ï¿½afe$ï¿½ï¿½ï¿½ P /ï¿½ï¿½Hï¿½ï¿½! ï¿½ï¿½'ï¿½ ^ï¿½~w .ï¿½2 ï¿½ ï¿½ï¿½ Cï¿½ ï¿½ BzM ï¿½ ï¿½ï¿½ ï¿½ï¿½ ï¿½ ï¿½? ;ï¿½ ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ ï¿½ï¿½ezLï¿½ï¿½ ï¿½@ï¿½ï¿½ï¿½ï¿½ 0ï¿½ï¿½ï¿½Nv ï¿½ ï¿½ï¿½ï¿½ï¿½ï¿½1ï¿½-j$7Rï¿½.ï¿½ï¿½7ï¿½$ï¿½ï¿½ï¿½ï¿½N s ï¿½ ï¿½ï¿½j ï¿½gï¿½fï¿½ \ï¿½/ï¿½j<ï¿½v( b'sZ4yï¿½Lï¿½ }>ï¿½ ï¿½ï¿½@W ï¿½ï¿½ï¿½ 6 ï¿½ 0ï¿½ ï¿½ï¿½ï¿½ï¿½tlhnï¿½<ï¿½Fï¿½ï¿½;@ -ï¿½ï¿½u ï¿½ï¿½ ï¿½?7 ï¿½( Eï¿½ A >4ï¿½ï¿½1ï¿½ï¿½sï¿½ ï¿½ T Iï¿½ Uï¿½ï¿½d1 ï¿½ï¿½+~Zï¿½[ï¿½- Kï¿½ï¿½ï¿½ *iAï¿½ï¿½ï¿½ ï¿½ï¿½ï¿½c?ï¿½[ï¿½ï¿½ï¿½ E ï¿½ï¿½ï¿½ï¿½ ï¿½ï¿½ Kï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ TI CodeComposer Studio syntax compatibility mode [default is %d] [default is %s] specify variant of 960 architecture -b add code to collect statistics about branches taken -link-relax preserve individual alignment directives so linker can do relaxing (b.out format only) -no-relax don't alter compare-and-branch instructions for long displacements specify variant of SPARC architecture -bump warn when assembler switches architectures -sparc ignored --enforce-aligned-data force .long, etc., to be aligned correctly -relax relax jumps and branches (default) -no-relax avoid changing any jumps and branches %s NDS32-specific assembler options: input file : %s options passed : output file : %s target : %s time stamp : %s -no-relax don't relax relocations D30V options: -O Make adjacent short instructions parallel if possible. -n Warn about all NOPs inserted by the assembler. -N Warn about NOPs inserted after word multiplies. -c Warn about symbols whose names match register names. -C Opposite of -C. -c is the default. TIC4X options: -mcpu=CPU -mCPU select architecture variant. CPU can be: 30 - TMS320C30 31 - TMS320C31, TMS320LC31 32 - TMS320C32 33 - TMS320VC33 40 - TMS320C40 44 - TMS320C44 -mrev=REV set cpu hardware revision (integer numbers). Combinations of -mcpu and -mrev will enable/disable the appropriate options (-midle2, -mlowpower and -menhanced) according to the selected type -mbig select big memory model -msmall select small memory model (default) -mregparm select register parameters (default) -mmemparm select memory parameters -midle2 enable IDLE2 support -mlowpower enable LOPOWER and MAXSPEED support -menhanced enable enhanced opcode support constraint violations for constraint violations instructions might violate constraints might violate constraints EXTENSION is combination of: Registers will not need any prefix. Registers will require a `$'-prefix. emulate output (default %s) Record the cpu type -EB assemble code for a big-endian cpu -EL assemble code for a little-endian cpu -FIXDD fix data dependencies -G gpnum assemble code for setting gpsize, default is 8 bytes -KPIC generate PIC -NWARN do not print warning message when fixing data dependencies -O0 do not perform any optimizations -SCORE3 assemble code for target SCORE3 -SCORE5 assemble code for target SCORE5 -SCORE5U assemble code for target SCORE5U -SCORE7 assemble code for target SCORE7 [default] -USE_R1 assemble code for no warning message when using temp register r1 -V Sunplus release version -V print assembler version number -Qy, -Qn ignored -march=score3 assemble code for target SCORE3 -march=score7 assemble code for target SCORE7 [default] S390 options: -mregnames Allow symbolic names for registers -mwarn-areg-zero Warn about zero base/index registers -mno-regnames Do not allow symbolic names for registers -m31 Set file format to 31 bit format -m64 Set file format to 64 bit format ops were: %s did you mean this? other valid variant(s): --32/--64/--x32 generate 32bit/64bit/x32 code --MD FILE write dependency information in FILE (default none) --alternate initially turn on alternate macro syntax --compress-debug-sections[={none|zlib|zlib-gnu|zlib-gabi}] compress DWARF debug sections using zlib --compress-debug-sections[={none|zlib|zlib-gnu|zlib-gabi}] compress DWARF debug sections using zlib [default] --debug-prefix-map OLD=NEW map OLD to NEW in debug information --defsym SYM=VAL define symbol SYM to given value --disp-size-default-22 branch displacement with unknown size is 22 bits (default) --disp-size-default-32 branch displacement with unknown size is 32 bits --divide do not treat `/' as a comment character --divide ignored --elf-stt-common=[no|yes] generate ELF common symbols with STT_COMMON type --execstack require executable stack for this object --fatal-warnings treat warnings as errors --fix-v4bx Allow BX in ARMv4 code --gdwarf-2 generate DWARF2 debugging information --gdwarf-sections generate per-function section names for DWARF line information --gstabs generate STABS debugging information --gstabs+ generate STABS debug info with GNU extensions --hash-size= set the hash table size close to --help show this message and exit --itbl INSTTBL extend instruction set to include instructions matching the specifications defined in file INSTTBL --listing-cont-lines set the maximum number of continuation lines used for the output data column of the listing --listing-lhs-width set the width in words of the output data column of the listing --listing-lhs-width2 set the width in words of the continuation lines of the output data column; ignored if smaller than the width of the first line --listing-rhs-width set the max width in characters of the lines from the source file --m32bit-doubles [default] --m32bit-doubles [default] --m64bit-doubles --m64bit-doubles Source code uses 64-bit doubles --march= Generate code for . Valid choices for are v0_v10, v10, v32 and common_v10_v32. --mbig-endian-data --mcpu= --mg10 Enable support for G10 variant --mg13 Selects the G13 core. --mg14 Selects the G14 core [default] --mint-register= --mlittle-endian-data [default] --mno-allow-string-insns --mpid --mrelax --mrelax Enable link time relaxation --mrl78 Alias for --mg14 --msmall-data-limit --muse-conventional-section-names --muse-renesas-section-names [default] --no-underscore User symbols do not have any prefix. --nocompress-debug-sections don't compress DWARF debug sections --nocompress-debug-sections don't compress DWARF debug sections [default] --noexecstack don't require executable stack for this object --pic Enable generation of position-independent code. --reduce-memory-overheads prefer smaller memory use at the cost of longer assembly times --sectname-subst enable section name substitution sequences --size-check=[error|warning] ELF .size directive check (default --size-check=error) --statistics print various measured statistics from execution --strip-local-absolute strip local absolute symbols --target-help show target specific options --traditional-format Use same format as native assembler when possible --underscore User symbols are normally prepended with underscore. --version print assembler version number and exit --warn don't suppress warnings -D produce assembler debugging messages -EB assemble code for a big-endian cpu -EB assemble for a big endian system (default) -EL assemble for a little endian system -EB,-big produce big endian code and data -EL generate code for little endian mode (default) -EB generate code for big endian mode -mwarn-expand warn if pseudo operations are expanded -mxp enable i860XP support (disabled by default) -mintel-syntax enable Intel syntax (default to AT&T/SVR4) -EL assemble code for a little-endian cpu -EL, -mel or -little Produce little endian output -EB, -meb or -big Produce big endian output -mpic Generate PIC -mno-fp-as-gp-relax Suppress fp-as-gp relaxation for this file -mb2bb-relax Back-to-back branch optimization -mno-all-relax Suppress all relaxation for this file -EL,-little produce little endian code and data -I DIR add DIR to search list for .include directives -Ip synonym for -ignore-parallel-conflicts -J don't warn about signed overflow -K warn when differences altered for long displacements -KPIC generate PIC -L,--keep-locals keep local symbols (e.g. starting with `L') -M,--mri assemble in MRI compatibility mode -N Warn when branches are expanded to jumps. -O try to optimize code. Implies -parallel -O1, Optimize for performance -Os Optimize for space -Q ignored -Q ignored -V print assembler version number -Q ignored -V print assembler version number -EB/-EL generate big-endian/little-endian code --32/--64 generate 32bit/64bit code -Q ignored -V print assembler version number -k ignored -R fold data section into text section -V print assembler version number -Qy, -Qn ignored -W --no-warn suppress warnings -Wnp synonym for -no-warn-explicit-parallel-conflicts -Wnuh synonym for -no-warn-unmatched-high -Wp synonym for -warn-explicit-parallel-conflicts -Wuh synonym for -warn-unmatched-high -X ignored -Z generate object file even after errors -c print a warning if a comment is found -f skip whitespace and comment preprocessing -fixed-special-register-names Allow only the original special register names. -g --gen-debug generate debugging information -globalize-symbols Make all symbols global. -gnu-syntax Turn off mmixal syntax compatibility. -h, -H Don't execute, print this help text. Deprecated. -h-tick-hex Support H'00 style hex constants -ignore-parallel-conflicts do not check parallel instructions -linker-allocated-gregs If there's no suitable GREG definition for the operands of an instruction, let the linker resolve. -m%s%s -m32r disable support for the m32rx instruction set -m32r2 support the extended m32r2 instruction set -m32rx support the extended m32rx instruction set -m4byte-align Mark the binary as using 32-bit alignment (default) -m8byte-align Mark the binary as using 64-bit alignment -mEA -mbarrel-shifter -mbarrel_shifter -mcrc -mdsp-packa -mdsp_packa -mdvbf -mld-extension-reg-mask -mlock -mmac-24 -mmac-d16 -mmac_24 -mmac_d16 -mmin-max -mmin_max -mmul64 -mno-mpy -mnorm -mrtsc -msimd -mswap -mswape -mtelephony -muser-mode-only -mxy -mN - do not insert NOPs after changing interrupts (default) -mQ - enable relaxation at assembly time. DANGEROUS! -mP - enable polymorph instructions -mY - do not warn about missing NOPs after changing interrupts -m[no-]%-17sEnable/Disable %s -mach= Set the H8300 machine type to one of: h8300h, h8300hn, h8300s, h8300sn, h8300sx, h8300sxn -madd-bnd-prefix add BND prefix for all valid branches -mall-ext Turn on all extensions and instructions support -mall-opcodes accept all AVR opcodes, even if not supported by MCU -mno-skip-bug disable warnings for skipping two-word instructions (default for avr4, avr5) -mno-wrap reject rjmp/rcall instructions with 8K wrap-around (default for avr3, avr5) -mrmw accept Read-Modify-Write instructions -mlink-relax generate relocations for linker relaxation (default) -mno-link-relax don't generate relocations for linker relaxation. -mgcc-isr accept the __gcc_isr pseudo-instruction. -mamd64 accept only AMD64 ISA -march=ARCH enable instructions from architecture ARCH -march=CPU[,+EXTENSION...] generate code for CPU and EXTENSION, CPU is one of: -march=ms1-16-002 allow ms1-16-002 instructions (default) -march=ms1-16-003 allow ms1-16-003 instructions -march=ms1-64-001 allow ms1-64-001 instructions -march=ms2 allow ms2 instructions -mavxscalar=[128|256] encode scalar AVX instructions with specific vector length -mbig-endian generate big-endian code -mbig-obj generate big object files -mcpu= specify the name of the target CPU -md - Force copying of data from ROM to RAM at startup -mdata-region={none|lower|upper|either} - select region data will be placed in. -mdsbt code uses DSBT addressing -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector length -mevexrcig=[rne|rd|ru|rz] encode EVEX instructions with specific EVEX.RC value for SAE-only ignored instructions -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value for EVEX.W bit ignored instructions -mextension enable extension opcode support -mfdpic assemble for the FDPIC ABI -mfence-as-lock-add=[no|yes] encode lfence, mfence and sfence as lock addl $0x0, (%%{re}sp) -mgcc-abi Mark the binary as using the old GCC ABI -mhard-float Mark the binary as using FP insns (default for e2v3 and up) -mindex-reg support pseudo index registers -mintel64 accept only Intel64 ISA -mip2022 restrict to IP2022 insns -mip2022ext permit extended IP2022 insn -ml - enable large code model -mlittle-endian generate little-endian code -mmnemonic=[att|intel] use AT&T/Intel mnemonic -mn - insert a NOP after changing interrupts -mnaked-reg don't require `%%' prefix for registers -mno-bcond17 disable b disp17 instruction -mno-dsbt code does not use DSBT addressing -mno-fdpic/-mnopic disable -mfdpic -mno-pic code addressing is position-dependent -mno-stld23 disable st/ld offset23 instruction -mold-gcc support old (<= 2.8.1) versions of gcc -momit-lock-prefix=[no|yes] strip all lock prefixes -moperand-check=[none|error|warning] check operand combinations for validity -mpic code addressing is position-independent -mpid=far code uses position-independent data addressing, GOT accesses use far DP addressing -mpid=near code uses position-independent data addressing, GOT accesses use near DP addressing -mpid=no code uses position-dependent data addressing -mrelax Enable relaxation -mrelax enable relaxation -mrelax-relocations=[no|yes] generate relax relocations -mrh850-abi Mark the binary as using the RH850 ABI (default) -mshared disable branch optimization for shared code -msilicon-errata=[,...] - enable fixups for silicon errata -msilicon-errata-warn=[,...] - warn when a fixup might be needed supported errata names: cpu4, cpu8, cpu11, cpu12, cpu13, cpu19 -msoft-float Mark the binary as not using FP insns (default for pre e2v3) -msse-check=[none|error|warning] check SSE instructions -msse2avx encode SSE instructions with VEX prefix -msyntax=[att|intel] use AT&T/Intel syntax -mtune=CPU optimize for CPU, CPU is one of: -mv850 The code is targeted at the v850 -mv850e The code is targeted at the v850e -mv850e1 The code is targeted at the v850e1 -mv850e2 The code is targeted at the v850e2 -mv850e2v3 The code is targeted at the v850e2v3 -mv850e2v4 Alias for -mv850e3v5 -mv850e3v5 The code is targeted at the v850e3v5 -mwarn-signed-overflow Warn if signed immediate values overflow -mwarn-unsigned-overflow Warn if unsigned immediate values overflow -my - warn about missing NOPs after changing interrupts (default) -n Do not optimize code alignment -q quieten some warnings -nIp synonym for -no-ignore-parallel-conflicts -no-bitinst disallow the M32R2's extended bit-field instructions -no-expand Do not expand GETA, branches, PUSHJ or JUMP into multiple instructions. -no-ignore-parallel-conflicts check parallel instructions for -no-merge-gregs Do not merge GREG definitions with nearby values. -no-pad-sections do not pad the end of sections to alignment boundaries -no-parallel disable -parallel -no-predefined-syms Do not provide mmixal built-in constants. Implies -fixed-special-register-names. -no-warn-explicit-parallel-conflicts do not warn when parallel -no-warn-unmatched-high do not warn about missing low relocs -nocpp ignored -nosched disable scheduling restrictions -o OBJFILE name the object-file output OBJFILE (default a.out) -parallel try to combine instructions in parallel -relax Create linker relaxable code. -s ignored -w ignored -warn-explicit-parallel-conflicts warn when parallel instructions -warn-unmatched-high warn when an (s)high reloc has no matching low reloc -x Do not warn when an operand to GETA, a branch, PUSHJ or JUMP is not known to be within range. The linker will catch any errors. Implies -linker-allocated-gregs. -xauto automagically remove dependency violations (default) -xnone turn off dependency violation checking -xdebug debug dependency violation checker -xdebugn debug dependency violation checker but turn off dependency violation checking -xdebugx debug dependency violation checker and turn on dependency violation checking @FILE read options from FILE %s; *input_line_pointer == '%c' 0x%02x AArch64-specific assembler options: ARM-specific assembler options: Blackfin specific assembler options: FR30 specific command line options: GNU assembler version %s (%s) using BFD version %s. H8300-specific assembler options: M32C specific command line options: M32R specific command line options: MMIX-specific command line options: Meta specific command line options: RL78 specific command line options: RX specific command line options: Score-specific assembler options: V850 options: XC16X specific command line options: XSTORMY16 specific command line options: Z8K options: -z8001 generate segmented code -z8002 generate unsegmented code -linkrelax create linker relaxable code branch relocation truncate (0x%x) [-2^9 ~ 2^9-1] branch relocation truncate (0x%x) [-2^19 ~ 2^19-1] branch relocation truncate (0x%x) [-2^9 ~ 2^9-1]!%s does not use a sequence number!samegp reloc against symbol without .prologue: %s"%d" (instance number %d of a %s label)".else" without matching ".if"".elseif" after ".else"".elseif" without matching ".if"".endif" without ".if"# Example of `%s' instructions .sect .text _start: # bars register# conflicts length#4 not valid on H8/300.###$DPR_BYTE not supported in this context$DPR_GOT not supported in this context$DPR_HWORD not supported in this context$DPR_WORD not supported in this context$DSBT_INDEX must be used with __c6xabi_DSBT_BASE$DSBT_INDEX not supported in this context$GOT not supported in this context$PCR_OFFSET not supported in this context$dbg and $depc are disabled when DEBUG is off$hi and $lo are disabled when MUL and DIV are off$mb0, $me0, $mb1, and $me1 are disabled when COP is off% operator needs absolute expression%%%s() must be outermost term in expression%%hi16/%%lo16 only applies to .short or .hword%%hi8 only applies to .byte%d error%d errors%d warning%d warnings%s %s -- `%s'%s -- statement `%s' ignored%s NOP inserted%s `%s' already has an alias `%s'%s argument must be a string%s at operand %d -- `%s'%s directive has no name%s for `%s'%s for instruction '%s'%s instruction does not accept a .b suffix%s instruction, operand %d doesn't match%s is enabled by vle flag%s is not used for the selected target%s may not occupy the delay slot of another branch insn.%s must be %d at operand %d -- `%s'%s must have a constant value%s not disabled by vle flag%s not supported in MIPS16 mode%s offset %d out of range%s offset %d out of range %d to %d%s out of domain (%d is not a multiple of %d)%s out of range %d to %d at operand %d -- `%s'%s out of range (%d is not between %d and %d)%s out of range (0x%s is not between 0x%s and 0x%s)%s register same as write-back base%s relocations do not fit in %d byte%s relocations do not fit in %d bytes%s relocations do not fit in %u byte%s relocations do not fit in %u bytes%s requires value 0-2 as operand 1%s second argument cannot be a negative number %d%s shortened to %s%s symbol recursion stopped at second appearance of '%s'%s unsupported%s unsupported as instruction fixup%s without %s%s, %s, generating bad object file %s, treating warnings as errors%s: attempt to rotate the PC register%s: global symbols not supported in common sections%s: no such section%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?%s: total time in assembly: %ld.%06ld %s: unexpected function type: %d%s: unrecognized processor name%s: would close weakref loop: %s%s:%u: bad return from bfd_install_relocation: %x%u-byte relocation cannot be applied to %u-byte field'%.*s' instruction not at start of execute packet'%.*s' instruction not in a software pipelined loop'%.*s' instruction not supported on this architecture'%.*s' instruction not supported on this functional unit'%.*s' instruction not supported on this functional unit for this architecture'%s' can't be a weak_definition (currently only supported in sections of type coalesced)'%s' can't be a weak_definition (since it is undefined)'%s' is not repeatable. Resulting behavior is undefined.'%s' is only available in DD2.0 or higher.'%s' may not be bundled with other instructions.'%s' previously declared as '%s'.'%s': only the NOP instruction can be issued in parallel on the m32r')' required',' expected'APSR', 'CPSR' or 'SPSR' expected'ASR' required'H' modifier only valid for accumulator registers'L' modifier not valid for this instruction'LSL' or 'ASR' required'LSL' required'MFC_RdTagMask' (channel 12) is only available in DD2.0 or higher.'P', 'N' or 'Z' flags may only be specified when accumulating'ROR' shift is not permitted'SPU_RdEventMask' (channel 11) is only available in DD2.0 or higher.'[' expected'[' expected after PLD mnemonic'[' expected after PLI mnemonic']' expected'd.%s' must be 8-byte aligned'entry_num' must be absolute number in [0,31]'||' after predicate'||' not followed by instruction'||^' without previous SPMASK'}' expected at end of 'option' field(PC)+ unpredictable(Requires %s; requested architecture is %s.)(plt) is only valid on branch targets(unknown reason)*-%s conflicts with the other architecture options, which imply -%s-(PC) unpredictable-- unterminated string--abi=[32|64] set size of expanded SHmedia operands and object file type --shcompact-const-crange emit code-range descriptors for constants in SHcompact code sections --no-mix disallow SHmedia code in the same section as constants and SHcompact code --no-expand do not expand MOVI, PT, PTA or PTB instructions --expand-pt32 with -abi=64, expand PT, PTA and PTB instructions to 32 bits only --absolute-literals option not supported in this Xtensa configuration--compress-debug-sections=%s is unsupported--density option is ignored--fdpic generate an FDPIC object file --generics is deprecated; use --transform instead--gstabs is not supported for ia64--hash-size needs a numeric argument--isa=[shmedia set as the default instruction set for SH64 | SHmedia | shcompact | SHcompact] --no-density option is ignored--no-generics is deprecated; use --no-transform instead--no-relax is deprecated; use --no-transform instead--no-underscore is invalid with a.out format--nops needs a numeric argument--pic is invalid for this object format--relax is deprecated; use --transform instead-32 create 32 bit object file -64 create 64 bit object file -32 create o32 ABI object file (default) -n32 create n32 ABI object file -64 create 64 ABI object file -EL generate code for a little endian machine -EB generate code for a big endian machine --little-endian-data generate code for a machine having big endian instructions and little endian data. -G may not be used in position-independent code-G may not be used with SVR4 PIC code-G may not be used with abicalls-G n Put data <= n bytes in the small data area -G not supported in this configuration-KPIC generate PIC -V print assembler version number -undeclared-regs ignore application global register usage without appropriate .register directive (default) -no-undeclared-regs force error on application global register usage without appropriate .register directive --dcti-couples-detect warn when an unpredictable DCTI couple is found -q ignored -Qy, -Qn ignored -s ignored -KPIC, -call_shared generate SVR4 position independent code -call_nonpic generate non-PIC code that can operate with DSOs -mvxworks-pic generate VxWorks position independent code -non_shared do not generate code that can operate with DSOs -xgot assume a 32 bit GOT -mpdr, -mno-pdr enable/disable creation of .pdr sections -mshared, -mno-shared disable/enable .cpload optimization for position dependent (non shared) code -mabi=ABI create ABI conformant object file for: -R option not supported on this target.-TSO use Total Store Ordering -PSO use Partial Store Ordering -RMO use Relaxed Memory Ordering -expand-pt32 invalid together with -no-expand-expand-pt32 only valid with -abi=64-k generate PIC -l use 1 word for refs to undefined symbols [default 2] -pic, -k generate position independent code -S turn jbsr into jsr --pcrel never turn PC-relative branches into absolute jumps --register-prefix-optional recognize register names without prefix character --bitwise-or do not treat `|' as a comment character --base-size-default-16 base reg without size is 16 bits --base-size-default-32 base reg without size is 32 bits (default) --disp-size-default-16 displacement with unknown size is 16 bits --disp-size-default-32 displacement with unknown size is 32 bits (default) -mCPU equivalent to -march=CPU -mtune=CPU. Deprecated. -no-mCPU don't generate code specific to CPU. For -mCPU and -no-mCPU, CPU must be one of: -mPIC Mark generated file as using large position independent code -m[no-]%-16s enable/disable %s architecture extension -maltivec generate code for AltiVec -mvsx generate code for Vector-Scalar (VSX) instructions -me300 generate code for PowerPC e300 family -me500, -me500x2 generate code for Motorola e500 core complex -me500mc, generate code for Freescale e500mc core complex -me500mc64, generate code for Freescale e500mc64 core complex -me5500, generate code for Freescale e5500 core complex -me6500, generate code for Freescale e6500 core complex -mspe generate code for Motorola SPE instructions -mspe2 generate code for Freescale SPE2 instructions -mvle generate code for Freescale VLE instructions -mtitan generate code for AppliedMicro Titan core complex -mregnames Allow symbolic names for registers -mno-regnames Do not allow symbolic names for registers -march=%s is not compatible with the selected ABI-march= set architecture -mcpu= set cpu [default %s] -mcpu= Specify the CPU version -mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat} -mdouble Mark generated file as using double precision FP insns -mdsp generate DSP instructions -mno-dsp do not generate DSP instructions -mdspr2 generate DSP R2 instructions -mno-dspr2 do not generate DSP R2 instructions -mdspr3 generate DSP R3 instructions -mno-dspr3 do not generate DSP R3 instructions -mdword Mark generated file as using a 8-byte stack alignment -me Redirect errors to a file -merrors-to-file -mfar-mode | -mf Use extended addressing -mfdpic Assemble for the FDPIC ABI -mfix-loongson2f-jump work around Loongson2F JUMP instructions -mfix-loongson2f-nop work around Loongson2F NOP errata -mfix-vr4120 work around certain VR4120 errata -mfix-vr4130 work around VR4130 mflo/mfhi errata -mfix-24k insert a nop after ERET and DERET instructions -mfix-cn63xxp1 work around CN63XXP1 PREF errata -mgp32 use 32-bit GPRs, regardless of the chosen ISA -mfp32 use 32-bit FPRs, regardless of the chosen ISA -msym32 assume all symbols have 32-bit values -O0 remove unneeded NOPs, do not swap branches -O remove unneeded NOPs and swap branches --trap, --no-break trap exception on div by 0 and mult overflow --break, --no-trap break exception on div by 0 and mult overflow -mfpr-32 Mark generated file as only using 32 FPRs -mfpr-64 Mark generated file as using all 64 FPRs -mgpr-32 Mark generated file as only using 32 GPRs -mgpr-64 Mark generated file as using all 64 GPRs -mhard-float allow floating-point instructions -msoft-float do not allow floating-point instructions -msingle-float only allow 32-bit floating-point operations -mdouble-float allow 32-bit and 64-bit floating-point operations --[no-]construct-floats [dis]allow floating point values to be constructed --[no-]relax-branch [dis]allow out-of-range branches to be relaxed -mignore-branch-isa accept invalid branches requiring an ISA mode switch -mno-ignore-branch-isa reject invalid branches requiring an ISA mode switch -mnan=ENCODING select an IEEE 754 NaN encoding convention, either of: -minsn32 only generate 32-bit microMIPS instructions -mno-insn32 generate all microMIPS instructions -mips1 generate MIPS ISA I instructions -mips2 generate MIPS ISA II instructions -mips3 generate MIPS ISA III instructions -mips4 generate MIPS ISA IV instructions -mips5 generate MIPS ISA V instructions -mips32 generate MIPS32 ISA instructions -mips32r2 generate MIPS32 release 2 ISA instructions -mips32r3 generate MIPS32 release 3 ISA instructions -mips32r5 generate MIPS32 release 5 ISA instructions -mips32r6 generate MIPS32 release 6 ISA instructions -mips64 generate MIPS64 ISA instructions -mips64r2 generate MIPS64 release 2 ISA instructions -mips64r3 generate MIPS64 release 3 ISA instructions -mips64r5 generate MIPS64 release 5 ISA instructions -mips64r6 generate MIPS64 release 6 ISA instructions -march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of: -mips16 generate mips16 instructions -no-mips16 do not generate mips16 instructions -mips16 cannot be used with -micromips-mlibrary-pic Mark generated file as using position independent code for libraries -mmcu generate MCU instructions -mno-mcu do not generate MCU instructions -mmedia Mark generated file as using media insns -mmicromips generate microMIPS instructions -mno-micromips do not generate microMIPS instructions -mmicromips cannot be used with -mips16-mmsa generate MSA instructions -mno-msa do not generate MSA instructions -mmt generate MT instructions -mno-mt do not generate MT instructions -mmuladd Mark generated file as using multiply add/subtract insns -mno-dword Mark generated file as using a 4-byte stack alignment -mno-pack Do not allow instructions to be packed -mnopic Disable -mpic, -mPIC, -mlibrary-pic and -mfdpic -mpack Allow instructions to be packed -mpic Mark generated file as using small position independent code -mppc64, -m620 generate code for PowerPC 620/625/630 -mppc64bridge generate code for PowerPC 64, including bridge insns -mbooke generate code for 32-bit PowerPC BookE -ma2 generate code for A2 architecture -mpower4, -mpwr4 generate code for Power4 architecture -mpower5, -mpwr5, -mpwr5x generate code for Power5 architecture -mpower6, -mpwr6 generate code for Power6 architecture -mpower7, -mpwr7 generate code for Power7 architecture -mpower8, -mpwr8 generate code for Power8 architecture -mpower9, -mpwr9 generate code for Power9 architecture -mcell generate code for Cell Broadband Engine architecture -mcom generate code for Power/PowerPC common instructions -many generate code for any architecture (PWR/PWRX/PPC) -mrelocatable support for GCC's -mrelocatble option -mrelocatable-lib support for GCC's -mrelocatble-lib option -memb set PPC_EMB bit in ELF flags -mlittle, -mlittle-endian, -le generate code for a little endian machine -mbig, -mbig-endian, -be generate code for a big endian machine -msolaris generate code for Solaris -mno-solaris do not generate code for Solaris -K PIC set EF_PPC_RELOCATABLE_LIB in ELF flags -V print assembler version number -Qy, -Qn ignored -msmartmips generate smartmips instructions -mno-smartmips do not generate smartmips instructions -msoft-float Mark generated file as using software FP -mtomcat-debug Debug tomcat workarounds -mtomcat-stats Print out stats for tomcat workarounds -mvirt generate Virtualization instructions -mno-virt do not generate Virtualization instructions -mxpa generate eXtended Physical Address (XPA) instructions -mno-xpa do not generate eXtended Physical Address (XPA) instructions -no-expand only valid with SHcompact or SHmedia-no-mix is invalid without specifying SHcompact or SHmedia-nops=count when aligning, more than COUNT nops uses a branch -ppc476-workaround warn if emitting data to code sections -shcompact-const-crange is invalid without SHcompact.%s outside of %s....COMMon length (%d.) < 0! Ignored..COMMon length (%ld.) <0! Ignored..COMMon length (%lu) out of range ignored.EQU must use a label.EXIT must appear within a procedure.REG expression must be a register.REG must use a label.SCOMMon length (%ld.) <0! Ignored..abiversion expression does not evaluate to a constant.abort detected. Abandoning ship..arch requires a matching --march=... option.asmfunc pseudo-op only available with -mccs flag..asmfunc repeated..asmfunc without function..begin [no-]density is ignored.begin directive with no matching .end directive.begin directive without a preceding .ent directive.begin directive without a preceding .file directive.begin literal is deprecated; use .literal instead.begin/.bend in different segments.bend directive names unknown symbol.bend directive without a preceding .ent directive.bend directive without a preceding .file directive.bss size %d < 0!.bss size %ld < 0!.bss size argument missing .bundle_align_mode alignment too large (maximum %u).bundle_lock is meaningless without .bundle_align_mode.bundle_lock sequence at %u bytes, but .bundle_align_mode limit is %u bytes.bundle_lock sequence is %u bytes, but bundle size is only %u bytes.bundle_lock with no matching .bundle_unlock.bundle_unlock without preceding .bundle_lock.callinfo is not within a procedure definition.cfi_endproc without corresponding .cfi_startproc.cfi_fde_data is not supported for this target.cfi_fde_data without corresponding .cfi_startproc.cfi_inline_lsda is not supported for this target.cfi_inline_lsda not valid for this frame.cfi_inline_lsda seen for frame without .cfi_lsda.cfi_lsda requires encoding and symbol arguments.cfi_personality requires encoding and symbol arguments.cfi_personality_id is not supported for this target.compiler directive missing language and version.compiler directive missing version.cpload not in noreorder section.def pseudo-op only available with -mccs flag..def pseudo-op used inside of .def/.endef: ignored..def pseudo-op used inside of .def/.endef; ignored.dim pseudo-op used outside of .def/.endef: ignored..dim pseudo-op used outside of .def/.endef; ignored.ef with no preceding .function.end [no-]density is ignored.end directive has no name.end directive missing or unknown symbol.end directive names different symbol than .ent.end directive names unknown symbol.end directive without a preceding .ent directive.end directive without a preceding .ent directive..end directive without a preceding .file directive.end directive without matching .ent.end not in text section.end symbol does not match .ent symbol.end symbol does not match .ent symbol..end%c encountered without preceding %s.end%s without preceding .%s.endasmfunc pseudo-op only available with -mccs flag..endasmfunc without a .asmfunc..endasmfunc without function..endef pseudo-op used before .def; ignored.endef pseudo-op used outside of .def/.endef: ignored..endfunc missing for previous .func.endfunc missing for previous .proc.ent directive has no name.ent directive has no symbol.ent directive without matching .end.ent or .aent not in text section.ent or .aent not in text section..err encountered.error directive invoked in source file.es without preceding .bs.fail %ld encountered.field count '%d' out of range (1 <= X <= 32).fill size clamped to %d.fmask outside of .ent.fnend directive without .fnstart.frame outside of .ent.gnu_attribute %d,%d is incompatible with `%s'.gnu_attribute %d,%d is no longer supported.gnu_attribute %d,%d is not a recognized floating-point ABI.gnu_attribute %d,%d requires `%s'.handler directive has no name.ifeqs syntax error.incbin count zero, ignoring `%s'.inst.n operand too big. Use .inst.w instead.largecomm supported only in 64bit mode, producing .comm.linkonce is not supported for this object file format.literal not allowed inside .begin literal region.literal_position inside literal directive; ignoring.ln pseudo-op inside .def/.endef: ignored..loc before .file.loc outside of .text.loc pseudo-op inside .def/.endef: ignored..localentry expression for `%s' does not evaluate to a constant.localentry expression for `%s' is not a valid power of 2.longcall pseudo-op seen when not relaxing.longjump pseudo-op seen when not relaxing.ltorg in section %s paired to .using in section %s.ltorg without prior .using in section %s.machine stack overflow.machine stack underflow.machinemode stack overflow.machinemode stack underflow.mask outside of .ent.mask/.fmask outside of .ent.module is not permitted after generating code.module used with unrecognized symbol: %s .name directive has no symbol.name directive not in link (.link) section.option pic%d not supported.option pic%d not supported in VxWorks PIC mode.option pop with no .option push.pdesc directive has no entry symbol.pdesc directive not in link (.link) section.pdesc doesn't match with last .ent.pdesc has a bad entry symbol.popsection without corresponding .pushsection; ignored.previous without corresponding .section; ignored.profiler pseudo requires at least two operands..prologue directive without a preceding .ent directive.prologue within prologue.ref outside .csect.ref pseudo-op only available with -mccs flag..sblock may be used for initialized sections only.scl pseudo-op used outside of .def/.endef: ignored..scl pseudo-op used outside of .def/.endef; ignored.sect: subsection name ignored.set pop with no .set push.set syntax invalid .size expression for %s does not evaluate to a constant.size pseudo-op used outside of .def/.endef: ignored..size pseudo-op used outside of .def/.endef; ignored.space or .fill with negative value, ignored.space repeat count is negative, ignored.space repeat count is zero, ignored.space specifies non-absolute value.space/.bes repeat count is negative, ignored.space/.bes repeat count is zero, ignored.stab%c is not supported.stab%c: description field '%x' too big, try a different debug format.stab%c: ignoring non-zero other field.stab%c: missing comma.stabx of storage class stsym must be within .bs/.es.syntax %s requires command-line option `--no-underscore'.syntax %s requires command-line option `--underscore'.tag pseudo-op used outside of .def/.endef: ignored..tag pseudo-op used outside of .def/.endef; ignored.tag requires a structure tag.tag target '%s' undefined.tc not in .toc section.tc with no label.type pseudo-op used outside of .def/.endef: ignored..type pseudo-op used outside of .def/.endef; ignored.unwind_save does not support this kind of register.usect: non-zero alignment flag ignored.usepv directive has no name.usepv directive has no type.uses does not refer to a local symbol in the same section.uses pseudo-op seen when not relaxing.uses target does not refer to a local symbol in the same section.using: base address expression illegal or too complex.val expression is too complex.val pseudo-op used outside of .def/.endef: ignored..val pseudo-op used outside of .def/.endef; ignored.var may only be used within a macro definition.vframepsp is meaningless, assuming .vframesp was meant.vliw unavailable when VLIW is disabled..warning directive invoked in source file.word %s-%s+%s didn't fit.word case-table handling failed: table too large0x%lx out range of signed 32bit displacement0x%lx: "%s" type = %ld, class = %d, segment = %d 128-bit SIMD scalar or floating-point quad precision register expected16-bit SIMD scalar or floating-point half precision register expected16-bit address isn't allowed in MPX instructions16-bit extension16-bit jump out of range16-bit relocation used in 8-bit operand3-bit immediate out of range32-bit SIMD scalar or floating-point single precision register expected32-bit address isn't allowed in 64-bit MPX instructions.32-bit conditional branch generated32bit mode not supported on `%s'.32bit x86_64 is only supported for ELF5-bit field must be absolute5-bit immediate too large6-bit displacement out of range6-bit immediate out of range62-bit relocation not yet implemented64-bit SIMD scalar or floating-point double precision register expected64-bit integer or SP register expected64bit mode not supported on `%s'.68040 and 68851 specified; mmu instructions may assemble incorrectly8-bit SIMD scalar register expected8-bit displacement out of range8-bit immediate out of range8-bit relocation used in 16-bit operand: Immediate value in cbcond is out of range.: Instruction requires frs2 and frsd must be the same register: PC-relative operand can't be a constant: TLS operand can't be a constant: There are only 32 f registers; [0-31]: There are only 32 single precision f registers; [0-31]: There are only 64 f registers; [0-63]: asr number must be between 0 and 31: crypto immediate must be between 0 and 31: expected register name ccr : expected register name pc : expected register name r0-r7 : expecting %asrN: expecting crypto immediate: imm2 immediate operand out of range (0-3): invalid ASI expression: invalid ASI name: invalid ASI number: invalid cpreg name: invalid membar mask expression: invalid membar mask name: invalid membar mask number: invalid prefetch function expression: invalid prefetch function name: invalid prefetch function number: invalid siam mode expression: invalid siam mode number: non-immdiate imm2 operand: processing macro, real opcode handle not found in hash: unrecognizable ancillary state register: unrecognizable hyperprivileged register: unrecognizable privileged register:b not permitted; defaulting to :w:lower16: not allowed in this instruction:operand has too many bits:operand value(%d) too big for constraint:unknown relocation constraint size:upper16: not allowed in this instruction specify for ABI Specify a abi version could be v1, v2, v2fp, v2fpp assemble for floating point ABI Assemble for architecture could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s assemble for architecture Assemble for baseline could be v2, v3, v3m assemble for CPU assemble for DSP architecture assemble for FPU architecture Specify a FPU configuration 0: 8 SP / 4 DP registers 1: 16 SP / 8 DP registers 2: 32 SP / 16 DP registers 3: 32 SP / 32 DP registers,X controls implicit insertion of IT instructions assemble for eabi version ? section flag ignored with G present@%s is not a complex relocation.@%s reloc is not supported with %d-bit output format@tls may not be used with "%s" operands@tls may only be used in last operandA bignum/flonum may not be a displacement: 0x%lx usedA branch offset requires 0 MOD 4 alignmentA jump instruction with long immediate detected at the end of the ZOL label @%sA parameter named `%s' already exists for macro `%s'A status register or status bit name is requiredA0.2,A0.3,A1.2,A1.3 required for QUICKRoT registerAAARG -> unhandled constant reloc: %dADD/SUB sp, sp #immADRADRL used for a symbol not defined in the same fileAR %d can only be accessed by %c-unitAR register not found in indirect referenceARC-specific assembler options: ARM register expectedARMv8.2 scalar fp16 instruction cannot be conditional, the behaviour is UNPREDICTABLEAUDIO ISA extensionAVR Assembler options: -mmcu=[avr-name] select microcontroller variant [avr-name] can be: avr1 - classic AVR core without data RAM avr2 - classic AVR core with up to 8K program memory avr25 - classic AVR core with up to 8K program memory plus the MOVW instruction avr3 - classic AVR core with up to 64K program memory avr31 - classic AVR core with up to 128K program memory avr35 - classic AVR core with up to 64K program memory plus the MOVW instruction avr4 - enhanced AVR core with up to 8K program memory avr5 - enhanced AVR core with up to 64K program memory avr51 - enhanced AVR core with up to 128K program memory avr6 - enhanced AVR core with up to 256K program memory avrxmega2 - XMEGA, > 8K, < 64K FLASH, < 64K RAM avrxmega3 - XMEGA, RAM + FLASH < 64K, Flash visible in RAM avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM avrtiny - AVR Tiny core with 16 gp registers Aborting because statement has "%s"Absolute PC-relative value in relaxation code. Assembler error.....Absolute value in relaxation code. Assembler error.....Accessing `%s' as thread-local objectAccessing function `%s' as thread-local objectAddend to unresolved symbol is not on word boundary.Addend to unresolved symbol not on word boundary.Address mode *+ARx is not allowed in memory-mapped register addressing. Resulting behavior is undefined.Address mode *+ARx is write-only. Results of reading are undefined.Address of immediate operandAddressing mode not implemented yet.Adjusted signed .word (%#lx) overflows: `switch'-statement too large.Adjusted signed .word (%ld) overflows: `switch'-statement too large.Alignment (%lu) too large: 15 assumed.Alignment must be a power of 2Alignment negative: 0 assumedAlignment negative: 0 assumed.Alignment too large: %d assumedAlignment too large: %d. assumedAlignment too large: %d. assumed.Alpha options: -32addr treat addresses as 32-bit values -F lack floating point instructions support -mev4 | -mev45 | -mev5 | -mev56 | -mpca56 | -mev6 | -mev67 | -mev68 | -mall specify variant of Alpha architecture -m21064 | -m21066 | -m21164 | -m21164a | -m21164pc | -m21264 | -m21264a | -m21264b these variants include PALcode opcodes An IMM instruction should not be present in the .s fileAn illegal use of delay slot detected at the end of the ZOL label @%sAn instruction was expanded (%s)Architecture mismatch on "%s %s".Architecture variants are: Argument of .vec_size is expected 4 or 16, actual: %d.Argument of .vec_size is not a constant.Argument to .BLOCK/.BLOCKZ must be between 0 and 0x3fffffffArgument to .even ignoredAssembler does not yet support PICAssembler messages: At least one PR argument expectedAt least two PR arguments expectedAttempt to purge non-existing macro `%s'Attempt to put a common symbol into set %sAttempt to put an undefined symbol into set %sAttempt to redefine register set `%s'Attribute name not recognised: %sAuto increment/decrement offset '%ld' is out of range.Auxiliary register AR0--AR7 required for indirectBALIGN immediate not 0, 1, 2 or 3 (%lu)BFD is out of sync with GAS, unhandled well-known section type `%s'BSPEC already active. Nesting is not supported.BSPEC without ESPEC.BSS length (%d) < 0 ignoredBSS length (%d.) <0! Ignored.BYTE expression not a pure numberBYTE expression not in the range 0..255Bad .fmask directiveBad .frame directive 1./2. paramBad .frame directive 3./4. paramBad .mask directiveBad .section directive: want a,s,w,x,M,S,G,T in stringBad COFF version '%s'Bad CPU version '%s'Bad RA (%d) register for .frameBad base register, using $%d.Bad call to MD_ATOF()Bad call to MD_NTOF()Bad call to md_atof ()Bad call to md_atof () - floating point formats are not supportedBad call to md_atof()Bad direct addressing construct %sBad displacement %d (require 0--255) Bad expression: @%s + %s.Bad opcode table, broken assembler.Bad opcode-table-option, check in file ns32k-opcode.hBad operandBad operand for a load instruction: <%s>Bad operand for a store instruction: <%s>Bad operand value: %sBad parameter list for macro `%s'Bad register nameBad register name %sBad register rangeBad relocation fixup type (%d)Bad relocation type: 0x%02xBad segment (should be absolute).Bad segment in expression.Bad sequence number: !%s!%sBad suffix after ':' use {b|w|d} Defaulting to dBad suffix, defaulting to dBadly formed address expressionBanked registers are not available with this architecture.Big number is too bigBig-endian R2 is not supported.Bignum not permitted in short literal. Immediate mode assumed.Bignum too big for %c format; truncatedBignum too big for longBit field out of rangeBoth arguments must be substitution symbolsBoth the_insn.HI and the_insn.LO are set : %sBrackets in operand field incorrectBranch to unaligned addressBroken assembler. No assembly attempted.Buggy opcode: `%s' "%s" C0 - C15 expectedC54x-specific command line options: CFI instruction used without previous .cfi_startprocCFI is not supported for this targetCFI state restore without previous rememberCPU version has already been setCPU11: PC is destination of SR altering instructionCPU12: CMP/BIT with PC destination ignores next instructionCPU13: SR is destination of SR altering instructionCPU19: Instruction setting CPUOFF must be followed by a NOPCPU8: Stack pointer accessed with an odd offsetCRIS-specific options: C_EFCN symbol for %s out of scopeCalling gen_cond_branch_32 for .arch common_v10_v32 Can not do %d byte %srelocationCan not do %d byte pc-relative pic relocationCan not do %d byte pc-relative relocationCan not do %d byte pc-relative relocation for storage type %dCan not do %d byte pic relocationCan not do %d byte relocationCan not do %d byte relocation for storage type %dCan not find match relax hint. Line: %dCan not represent %s relocation in this object file formatCan not set dlx_skip_hi16_flagCan't add stop bit to mark end of instruction groupCan't change spaces within a procedure definition. IgnoredCan't change subspaces within a procedure definition. IgnoredCan't deal with expression; defaulting to %ldCan't do flonum short literal: immediate mode used.Can't find opcode to match operandsCan't handle O_big in s390_exp_compareCan't hash %s: %sCan't hash `%s': %s Can't hash instruction '%s':%sCan't redirect stderr to the file '%s'Can't relax differenceCan't relocate expressionCan't set GP valueCan't set register masksCan't use long branches on this architectureCan't work out size of operand. Cannot allocate unwind descriptor Cannot assemble instructionCannot define export symbol: %s Cannot define static symbol: %s Cannot express %s%d%s relocationCannot find relocation type for symbol %s, code %dCannot generate relocation type for symbol %s, code %sCannot handle fixupCannot make %s relocation PC relativeCannot represent %s relocation in object fileCannot represent exponent in %d bitsCannot represent relocation type %sCannot use POPM to restore the SR registerCannot use special register with this instructionCase value %ld unexpected at line %d of file "%s" Changing of CPU version on the fly not supportedChanging processor generation on fly not supported...Chose GP value of %lx Closing bracket missingComma and symbol expected for '.asg STRING, SYMBOL'Comma and symbol expected for '.eval EXPR, SYMBOL'Comma expectedComma expected Comma expected after section nameCommand-line value overrides ".cpu" directiveCommon alignment negative; 0 assumedCommon alignment not a power of 2Complex expression not supportedComplicated LAPC target operand is not a multiple of two. Use LAPC.DCondition "%s" does not match preceding groupCondition "%s" uses a different accumulator from a preceding conditionCondition <%c%c> in structured control directive can not be encoded correctlyConstant expression %d out of range, [%d, %d].Conversion of PC relative BSR to absolute JSRConversion of PC relative branch to absolute jumpConversion of PC relative conditional branch to absolute jumpConversion of PC relative displacement to absoluteCopyright (C) 2018 Free Software Foundation, Inc. Could not set architecture and machineCould not set architecture and machine.Couldn't generate extension instruction opcodesCreating sections with .xdataN/.xrealN/.xstringZ is deprecated.Current section is uninitialized, section name required for .clinkD register out of range for selected VFP versionD10V options: -O Optimize. Will do some operations in parallel. --gstabs-packing Pack adjacent short instructions together even when --gstabs is specified. On by default. --no-gstabs-packing If --gstabs is specified, do not pack adjacent instructions together. DSP RAM pointer in incorrect unitDangerous simultaneous use of `f%d' and `f%d'Default target `%s' is not supported.Defective assembler. No assembly attempted.Delayed branches not available on SH1Deprecated syntax.Destination accumulator for each part of this parallel instruction must be differentDestination register must be ARnDestination register must be R0 or R1Destination register must be R2 or R3Difference of symbols in different sections is not supportedDifferent arguments of .vec_size are found, previous %d, current %dDirect value of %ld is not suitableDirective .atmp available only with -mintel-syntax optionDirective .dual available only with -mintel-syntax optionDirective .enddual available only with -mintel-syntax optionDirective invalid within a bundleDisplacement length %s ignored!Displacement too large for :dDisplacement value of %ld is too largeDivide instructions supportDon't know how to figure out width of %c in md_assemble()Don't know how to handle this field. %sDon't know how to relocate plain operands of type %sDot Product instructions cannot be conditional, the behaviour is UNPREDICTABLEDuplicate %s conditionalDuplicate equal sign (=) in instructionDuplicate predicate register ignoredDuplicated pseudo-opcode %s.EBCDIC constants are not supportedECOFF debugging is disabled.ENDLOOP without corresponding LOOPEPIPHANY specific command line options: ESPEC without preceding BSPECEmpty argument of .endpEmpty argument of .procEpilogue count of %lu exceeds number of nested prologues (%u)Equal parallel destination registers, one result will be discardedError %s in %s Error in argument %d. Expecting: "%s"Error in expressionError in relocation handlingError in statement syntaxError setting flags for "%s": %sError: Even number required. Rounded to %dExecuting %s in IU in reverse serial may not workExecuting %s in IU may not workExecuting %s in IU may not work in parallel executionExecuting %s in reverse serial with %s may not workExpanded opcode after delayed branch: `%s'Expanded opcode in dual mode: `%s'Expected '('Expected ')'Expected ':'Expected '['Expected ']'Expected comma after common lengthExpected comma after nameExpected comma after name "%s"Expected comma after symbol-nameExpected comma after symbol-name: rest of line ignored.Expected immediate expressionExpected quoted stringExpected register, got '%s'.Expected separator `='Expected simple number.Expecting a constant valueExpecting a register nameExpecting a register.Expecting character constant argumentExpecting comma after CPU errata name, not: %sExpecting operand after ','Expecting operand after ','; got nothingExpecting operand before ','; got nothingExpecting register D for indexed indirect mode.Expecting second argumentExplicit stops are ignored in auto modeExpression Error for operand modifier %%hi/%%lo Expression inside %%%s could not be parsedExpression out of range, using 0Expression too complex.Extended addressing not supported on the specified CPUExtra )Extra junk in function call, expecting ')'Extra junk on lineFATAL: Attaching compiler header %sFIRST not supported as a .SUBSPACE argumentFP branch in delay slotFP branch preceded by FP instruction; NOP insertedFPA .unwind_save does not take a register listFPA register expectedFPU DP extensionFPU SP extensionFPU fused-multiply-add instructionsFRAME parameter must be a multiple of 8: %d FRV specific command line options: FT32 options: Failed to create property section `%s' Failed to find a valid mode for `%s'.Failed to find real start of function: %s Fatal error: Field not properly aligned [%d] (%d).Field out of range [%d..%d] (%d).File '%s' not in macro archive formatFirst opcode is long. Unable to mix instructions as specified.First operand to .%s must be a predicateFirst operand to .%s not a registerFirst operand to .%s not a valid registerFirst operand to .altrp not a valid branch registerFirst operand to .fframe must be a constantFirst operand to .prologue must be a positive 4-bit constantFirst operand to .restore must be stack pointer (sp)First operand to .save not a registerFirst operand to .save not a valid registerFirst operand to .save.b must be a positive 5-bit constantFirst operand to .save.g must be a positive 4-bit constantFirst operand to .save.gf must be a non-negative 4-bit constantFirst operand to .unwabi must be a constantFirst operand to .vframe must be a general registerFix data dependency: %s %s -- %s %s (insert %d nop!/%d)Fix data dependency: %s %s -- %s %s (insert 1 pflush/%d)Fixup of %ld too large for field width of %dFloat AC not legal as integer operandFloating point number not valid in expressionFloating point register in register listForced short literal to immediate mode. now_seg=%s to_seg=%sForcing byte displacementFound '{' after explicit switch to automatic modeFound '{' when already bundling.Found '{' when manual bundling is already turned onFound '}' when manual bundling is offFound '}' when not bundling.Found use of non-canonical register name %s; use %s instead.Freescale XGATE co-processor options: -mshort use 16-bit int ABI (default) -mlong use 32-bit int ABI -mshort-double use 32-bit double ABI -mlong-double use 64-bit double ABI (default) --mxgate specify the processor variant [default %s] --print-insn-syntax print the syntax of instruction in case of error --print-opcodes print the list of instructions with syntax --generate-example generate an example of each instructionFunction expects two argumentsGNU assembler %s GNU assembler version %s (%s) using BFD version %s GOT already in symbol tableGOT already in the symbol tableGOT bad expression with %s.GP prologue size exceeds field size, using 0 insteadGREG expression too complicatedGarbage at end of instruction: `%s'.Gas failure, reloc type #%i Gas failure, reloc type %s Gas failure, reloc value %d General register not legal as float operandGroup section `%s' has no group signatureHI/LO registers should be specified togetherHI/LO registers should be specified without additional registersHardware capability "%s" not enabled for "%s".Hashing returned "%s".Hi-register ADD, MOV, CMP using pcHi-register ADD, MOV, CMP, BX, BLX using pcI don't need or use temp. file "%s".I don't use an interpass file! -V ignoredI960 options: IA-64 options: --mconstant-gp mark output file as using the constant-GP model (sets ELF header flag EF_IA_64_CONS_GP) --mauto-pic mark output file as using the constant-GP model without function descriptors (sets ELF header flag EF_IA_64_NOFUNCDESC_CONS_GP) -milp32|-milp64|-mlp64|-mp64 select data model (default -mlp64) -mle | -mbe select little- or big-endian byte order (default -mle) -mtune=[itanium1|itanium2] tune for a specific CPU (default -mtune=itanium2) -munwind-check=[warning|error] unwind directive check (default -munwind-check=warning) -mhint.b=[ok|warning|error] hint.b check (default -mhint.b=error) -x | -xexplicit turn on dependency violation checking IP2K specific command line options: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: %sIT blocks containing 32-bit Thumb instructions are deprecated in ARMv8IT blocks containing more than one conditional instruction are deprecated in ARMv8IT falling in the range of a previous IT blockIU instruction may not be in the left containerIgnoring attempt to re-define symbolIgnoring attempt to re-define symbol %sIgnoring attempt to re-define symbol `%s'.Ignoring attempt to spill beyond end of regionIgnoring changed section attributes for %sIgnoring statement due to "%s"Illegal 32 bit - processor register (`%s') in Instruction: `%s'Illegal AR register in indirect referenceIllegal Scale - `%d'Illegal `cinv' parameter: `%c'Illegal `mask16' operand, operation is undefined - `%s'Illegal co-processor register in instruction `%s'Illegal co-processor special register in instruction `%s'Illegal combination of relocation functionsIllegal emulated instructionIllegal index register pair (`%s') in Instruction: `%s'Illegal instruction or not implemented opcode.Illegal operand (arg %d)Illegal operand separator `%c'Illegal operand.Illegal operandsIllegal operands (whitespace): `%s'Illegal operands for %sIllegal operands%sIllegal operands: %%%s can be only used with call __tls_get_addrIllegal operands: %%%s cannot be used together with other relocs in the insn ()Illegal operands: %%%s requires arguments in ()Illegal operands: %%r_%s%d requires arguments in ()Illegal operands: %%r_plt in %d-byte data fieldIllegal operands: %%r_tls_dtpoff in %d-byte data fieldIllegal operands: %%tls_ldo in %d-byte data fieldIllegal operands: %%tls_ldo requires arguments in ()Illegal operands: Can't add non-constant expression to %%%s()Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbolIllegal operands: Can't do arithmetics other than + and - involving %%%s()Illegal operands: Only %%r_%s%d allowed in %d-byte data fieldsIllegal operands: garbage after %%r_%s%d()Illegal operands: garbage after %%tls_ldo()Illegal processor register (`%s') in Instruction: `%s'Illegal register (`%s') in Instruction: `%s'Illegal register (`%s') in instruction: `%s'Illegal register `%s' in Instruction `%s'Illegal register `%s' in cop-register listIllegal register `%s' in cop-special-register listIllegal register `%s' in instruction `%s'Illegal register `%s' in register listIllegal register `%s' in user register listIllegal register pair (`%s') in Instruction: `%s'Illegal register pair `%s' in Instruction `%s'Illegal section name `%s' (causes unwind section name clash)Illegal type of operand (arg %d)Immediate operand is not allowed for operand %d.Immediate value %ld too largeImmediate value for mbar > 32. using Immediate value not in 16 bit range: %ldImmediate value not in 16 bit signed range: %ldImmediate value not in 16 bit unsigned range: %ldImmediate value not in 4 bit unsigned range: %ldImmediate value not in 5 bit unsigned range: %ldImmediate value not in 6 bit range: %ldImmediate value not in 6 bit unsigned range: %ldImmediate value not in 8 bit range: %ldImmediate value not in 8 bit signed range: %ldImmediate value not in 8 bit unsigned range: %ldImmediate value of %ld is too largeImmediate value of %ld is too large for ldfImmediates %d and %d will give undefined behavior.Improper CSR address (%lu)Improper CSRxI immediate (%lu)Improper shift amount (%lu)Improper use of OP1_IMM_IMPLIEDImproper use of OP1_MUST_BE_IMMIncompatible first and second operands in instructionIncorrect fr_opcode value in frag. Internal error.....Incorrect number of operandsIncorrect number of operands givenIncorrect syntax, %s.Increment/decrement value is out of range: `%ld'.Index can only be applied to rotating or indirect registersIndex must be a general registerIndex out of range 0..%uIndex register IR0,IR1 required for displacementIndexed indirect mode is not allowed for movb/movw.Indirect indexed addressing is not valid for 68HC11.Indirect register index must be a general registerInfinite loop encountered whilst attempting to compute the addresses of symbols in section %sInfinities are not supported by this target Info: Initial .body should precede any instructionsInitial .prologue should precede any instructionsInserting "%s" into address type table failed: %sInserting "%s" into constant hash table failed: %sInserting "%s" into entry hint table failed: %sInserting "%s" into register table failed: %sInserting "%s" into structure table failed: %sInsn %s has a jump/branch instruction %s in its delay slot.Insn %s has an instruction %s with limm in its delay slot.Insn slot not set in unwind record.Instruction %s not allowed in a delay slot.Instruction %s not supported in the baseline.Instruction %s requires absolute expressionInstruction '%s' requires an LP cpu versionInstruction '%s' requires far mode addressingInstruction `%s' is not recognized.Instruction does not fit in available delay slots (%d-word insn, %d slot left)Instruction does not fit in available delay slots (%d-word insn, %d slots left)Instruction does not fit in available delay slots (%d-word insn, %d slot left). Resulting behavior is undefined.Instruction does not fit in available delay slots (%d-word insn, %d slots left). Resulting behavior is undefined.Instruction does not support =N addressesInstruction form not available on this architecture.Instruction formats for `%s':Instruction in R container is squashed by flow control instruction in L container.Instruction must be executed in parallelInstruction must be executed in parallel with another instruction.Instruction not supported by this architectureInstruction uses long version, so it cannot be mixed as specifiedInstructions do not use parallel execution pipelines.Instructions may not be executed in parallelInstructions share the same execution pipelineInstructions using long offset modifiers or absolute addresses are not repeatable. Resulting behavior is undefined.Instructions which cause PC discontinuity are not allowed in a delay slot. Resulting behavior is undefined.Intel K1OM is 64bit ELF onlyIntel K1OM is 64bit onlyIntel L1OM is 64bit ELF onlyIntel L1OM is 64bit onlyIntel MCU doesn't support `%s' architectureIntel MCU is 32bit ELF onlyIntel MCU is 32bit onlyInternal Error: Can't hash %s: %sInternal Error: Can't find %s in hash tableInternal Error: Can't hash %s: %sInternal Error: bad instruction lengthInternal assembler error for instruction %sInternal assembler error for instruction format %sInternal assembler error for macro %sInternal bug. Try to use 0(r%d) instead of @r%dInternal consistency error. check ns32k-opcode.hInternal error (%s). Internal error at %s:%d. Internal error found in md_convert_frag: offset %ld. Please report this.Internal error in %s at %s:%d. Internal error: Can't hash %s: %sInternal error: Range error. %sInternal error: Relax hint error. %s: %xInternal error: Unable to find containing space for %s.Internal error: Unknown fixup type %d (`%s')Internal error: can't find opcode `%s' for `%s' Internal error: can't hash `%s': %s Internal error: don't know how to force %s to end of instruction groupInternal error: losing opcode: `%s' "%s" Internal logic error in iif.iifP[].typeInternal logic error in iif.iifP[n].typeInternal logic error. Line %d, file: "%s"Internal logic error. line %d, file "%s"Invalid --compress-debug-sections option: `%s'Invalid --elf-stt-common= option: `%s'Invalid --size-check= option: `%s'Invalid .CALL argument: %sInvalid .CALLINFO argument: %sInvalid .SPACE argumentInvalid .SUBSPACE argumentInvalid .insn format Invalid Add Condition: %sInvalid Add and Branch ConditionInvalid Branch On Bit Condition: %cInvalid COPR identifierInvalid CST4 operand value (arg %d)Invalid Compare and Branch ConditionInvalid Compare/Subtract ConditionInvalid Compare/Subtract Condition: %sInvalid DISPU4 operand value (arg %d)Invalid DataLabel expressionInvalid FP Compare Condition: %sInvalid FP Operand Format: %3sInvalid FTEST completer: %sInvalid Floating Point Operand Format.Invalid Indexed Load Completer Syntax.Invalid Indexed Load Completer.Invalid Logical Instruction Condition.Invalid Nullification: (%c)Invalid PIC expression.Invalid SFU identifierInvalid Shift/Extract/Deposit Condition.Invalid Short Load/Store Completer.Invalid Store Bytes Short CompleterInvalid Unit Instruction Condition.Invalid accumulator register.Invalid argument %d to .prologue.Invalid argument description: %dInvalid argument location: %s Invalid argument to --abi option: %sInvalid argument to --isa option: %sInvalid argument to --mach option: %sInvalid argument to .abi: %sInvalid argument to .mode: %sInvalid auxiliary register (use AR0-AR7)Invalid character %s before %s operandInvalid character %s in %s operandInvalid character %s in opcodeInvalid combination of instructions for bundle.Invalid combination: --abi=32 with --abi=64Invalid combination: --abi=64 with --abi=32Invalid combination: --abi=64 with --isa=SHcompactInvalid combination: --isa=SHcompact with --abi=64Invalid combination: --isa=SHcompact with --isa=SHmediaInvalid combination: --isa=SHmedia with --isa=SHcompactInvalid constant operand %sInvalid default architecture, broken assembler.Invalid destination register for this instruction, use 'tfr'.Invalid destination register.Invalid directiveInvalid displacement in indirect referenceInvalid dmad syntax '%s'Invalid duplicate use of `%c%d'Invalid expression after # number Invalid expression after %%%% Invalid expression.Invalid field selector. Assuming F%%.Invalid field size, must be from 1 to 32Invalid floating point numberInvalid immediate write operand.Invalid indexed indirect mode.Invalid indexed register, expecting register X.Invalid indexed register, expecting register Y.Invalid indexed register.Invalid indirect addressing modeInvalid indirect addressing mode displacement %dInvalid instruction %sInvalid label '%s'Invalid left/right combination completerInvalid length (use 0 to %d)Invalid mnemonic '%s'Invalid mode: %s Invalid numberInvalid opcode/operandsInvalid operand (s) for parallel instruction "%s"Invalid operand (use 1, 2, or 3)Invalid operand expressionInvalid operand for `%s'Invalid operand: immediate value used as address.Invalid operand: immediate value used as base address.Invalid operandsInvalid operands %sInvalid operands for %sInvalid operation on symbolInvalid operator for operand.Invalid or illegal addressing mode combined with scaled-indexInvalid pc-relative relocationInvalid permutation completerInvalid record type for P3 format.Invalid record type for format B1Invalid record type for format P6Invalid record type for format X1Invalid record type for format X3Invalid register for dbcc/tbcc instruction.Invalid register for post/pre increment.Invalid register for single precision fmpyadd or fmpysubInvalid register in register listInvalid register list for ldm/stm Invalid register number at '%.6s'Invalid register specification.Invalid register.Invalid register: 'r%d'Invalid register: r0 and r15 illegalInvalid relocationInvalid scaled-indexed mode, use (b,w,d,q)Invalid simultaneous use of `f%d' and `f%d'Invalid source register for this instruction, use 'tfr'.Invalid source register.Invalid status register "%s"Invalid subscript (use 1 to %d)Invalid suffix for literal pool entryInvalid syntax in External addressing modeInvalid syntax in Memory Relative addressing modeInvalid syntax in PC-relative addressing modeInvalid use of `%c%d' as output operandInvalid use of `r%d' as base update address operandInvalid use of parallelization operator.JALX to a symbol in the same ISA modeJump/Branch instruction detected at the end of the ZOL label @%sJunk after '}': '%s'Junk at end of line, %s.Kernel instruction detected at the end of the ZOL label @%sKnown MCU names:LDP instruction needs a 24-bit operandLOC expression stepping backwards is not supportedLOC to section unknown or indeterminable at first passLR and PC should not both be in register listLabel "$%d" redefinedLabel "%s" matches a CPU register nameLabel must be first in a bundleLabel required for .tagLeading plus sign not allowed in core modeLength of .comm "%s" is already %ld. Not changed to %d.Length of .comm "%s" is already %ld. Not changed to %ld.Length of .lcomm "%s" is already %ld. Not changed to %ld.Length of .scomm "%s" is already %ld. Not changed to %ld.Length specification ignored. Address mode 9F usedLine %d: unknown relocation type: 0x%x.Line numbers must be positive integers Literal Pool OverflowLiteral loadsLong instructions may not be combined.Looks like a proc, but can't tell what kind. Low order bits truncated in immediate float operandM340 specific opcode used when assembling for M210MCORE specific options: -{no-}jsri2bsr {dis}able jsri to bsr transformation (def: dis) -{no-}sifilter {dis}able silicon filter behavior (def: dis) -cpu=[210|340] select CPU type -EB assemble for a big endian system (default) -EL assemble for a little endian system MCU option requires a name MDRD value must be between 1 and 8MIPS PIC call to register other than $25MIPS options: -EB generate big endian output -EL generate little endian output -g, -g2 do not remove unneeded NOPs or swap branches -G NUM allow referencing objects up to NUM bytes implicitly with the gp register [default 8] MN10200 options: none yet MN10300 assembler options: none yet MOVI operand is not a 32-bit signed value: 0x%8x%08xMRI style ORG pseudo-op not supportedMSP430 options: -mmcu= - select microcontroller type -mcpu={430|430x|430xv2} - select microcontroller architecture MT specific command line options: MU instruction may not be in the right containerMacro %s not implementedMacro `%s' was already definedMaverick DSPSC register expectedMaverick MVAX register expectedMaverick MVD register expectedMaverick MVDX register expectedMaverick MVF register expectedMaverick MVFX register expectedMaximum %d bits may be set in `mask16' operandMeP specific command line options: -EB assemble for a big endian system -EL assemble for a little endian system (default) -mconfig= specify a chip configuration to use -maverage -mno-average -mmult -mno-mult -mdiv -mno-div -mbitops -mno-bitops -mleadz -mno-leadz -mabsdiff -mno-absdiff -mminmax -mno-minmax -mclip -mno-clip -msatur -mno-satur -mcop32 enable/disable the given opcodes If -mconfig is given, the other -m options modify it. Otherwise, if no -m options are given, all core opcodes are enabled; if any enabling -m options are given, only those are enabled; if only disabling -m options are given, only those are disabled. Memory mapped register "%s" out of rangeMiscellaneous 16-bit instructionsMisplaced .entry. Ignored.Missing '(' after substitution symbol functionMissing ')'Missing ')' in subscripted substitution symbol expressionMissing ','Missing '}' at end of fileMissing '}': '%s'Missing )Missing ) in ra(rb)Missing .EXIT for a .ENTRYMissing .callinfoMissing .callinfo for this procedureMissing .callinfo.Missing .endp after previous .procMissing .exit Missing .label_state %ldMissing .procend Missing Branch On Bit ConditionMissing `]' to close indexed-indirect mode.Missing `]' to close register indirect operand.Missing arguments for opcode <%s>.Missing forced substitution terminator ':'Missing function name for .PROCMissing function name for .PROC (corrupted label chain)Missing label name on .LABELMissing macro nameMissing matching brackets : `%s'Missing operandMissing operand.Missing or bad .using directiveMissing parameter qualifier for `%s' in macro `%s'Missing predicate relation typeMissing second register for indexed-indirect mode.Missing second register or offset for indexed-indirect mode.Missing section nameMissing size argumentMissing symbol name in directiveMissing value for required parameter `%s' of macro `%s'Mixing of normal and extended addressing not supportedMixing register syntax, with and without '$'.More than one AR register found in indirect referenceMore than one displacement found in indirect referenceMore than one relocation op per insnMotorola 68HC11/68HC12/68HCS12 options: -m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg specify the processor [default %s] -mshort use 16-bit int ABI (default) -mlong use 32-bit int ABI -mshort-double use 32-bit double ABI -mlong-double use 64-bit double ABI (default) --force-long-branches always turn relative branches into absolute ones -S,--short-branches do not turn relative branches into absolute ones when the offset is out of range --strict-direct-mode do not turn the direct mode into extended mode when the instruction does not support direct mode --print-insn-syntax print the syntax of instruction in case of error --print-opcodes print the list of instructions with syntax --xgate-ramoffset offset ram addresses by 0xc000 --generate-example generate an example of each instruction (used for testing) Multiple .cpu directives foundMultiply instructions supportMust be in a space before changing or declaring subspaces. NOP inserted between two instructions that change interrupt stateNS32K options: -m32032 | -m32532 select variant of NS32K architecture --disp-size-default=<1|2|4> NaNs are not supported by this target Name # Modes Min ops Max ops Modes mask # Used Nan, using zero.Need #1 or #2 hereNeon double or quad precision register expectedNeon quad precision register expectedNeon single or double precision register expectedNested proceduresNo !literal!%ld was foundNo !tlsgd!%ld was foundNo !tlsldm!%ld was foundNo 'bal' entry point for leafproc %sNo .ENTRY for this .EXITNo addend allowed in @fptr() relocationNo comma after .pdesc No compiled in support for %d bit object file formatNo current frameNo instruction foundNo instruction or missing opcode.No lda !gpdisp!%ld was foundNo ldah !gpdisp!%ld was foundNo operatorNo relocation operandNo segment info for current sectionNo such entry in list. (cpu/mmu register)No such opcodeNo symbol after .code_addressNo symbol after .linkageNo valid label relocation operandNon-absolute symbol: '%s'.Non-constant symbols not allowed Non-global symbol: '%s' can't be a weak_definition.Not a defined coldfire architectureNot a function typeNot a symbolic expressionNot enough operandsNot in a space. Not in a subspace. Number of elements must be positiveNumber too largeOPF immediate operand out of range (0-0x1ff)Odd numbered register used as target of multi-register instructionOffset on nested structures is ignoredOffset out of 16-bit range for movw/movb insn: %ldOffset out of 16-bit range: %ld.Offset out of 5-bit range for movw/movb insn: %ldOffset out of 5-bit range for movw/movb insn: %ld.Offset out of 9-bit range for movw/movb insn: %ldOne of these instructions may not be executed in parallel.Only constant offsets are supportedOnly constant space allocation is supportedOnly one .compiler pseudo-op per file!Only one .copyright pseudo-op per file!Only one .version pseudo-op per file!Only one comparison conditional allowedOnly one overflow conditional allowedOnly the first path encountering the conflict is reportedOpcode %s not available in this modeOpcode `%s' is not recognized.Opcode `%s' with these operand types not available in %s modeOpcode `%s' with these operand types not available in H8/300 modeOpcode `%s' with these operand types not available in H8/300H modeOpcode `%s' with these operand types not available in H8/300S modeOpcode(%d.%s): Operand "%s" out of range (use 1 or 2)Operand %d to .%s must be a constantOperand %d to .%s must be a preserved registerOperand %d to .%s must be a writable registerOperand %u of `%s' should be %sOperand '%s' out of range (%d <= x <= %d)Operand `%x' not recognized in fixup16.Operand `%x' not recognized in fixup8.Operand has odd displacement (arg %d)Operand is not a constant. `%s'Operand mismatchOperand of .vframe contradicts .prologueOperand out of 16-bit range: `%ld'.Operand out of 8-bit range: `%ld'.Operand out of range (arg %d)Operand out of range for a relative branch: `%ld'Operand out of range, %s.Operand to .copy_state must be a constantOperand to .label_state must be a constantOperand to .save.f must be a positive 20-bit constantOperand to .spill must be a constantOperand to .vframesp must be a constant (sp-relative offset)Operand value is not within upper 64 KB (arg %d)Operands to .save.gf may not be both zeroOperator may only be applied to symbols.Option -b is depreciated, please use -mbigOption -p is depreciated, please use -mmemparmOption -r is depreciated, please use -mregparmOption -s is depreciated, please use -msmallOption `%s' is not recognized.Options: -a[sub-option...] turn on listings Sub-options [default hls]: c omit false conditionals d omit debugging directives g include general info h include high-level source l include assembly m include macro expansions n omit forms processing s include symbols =FILE list to FILE (must be last sub-option) Out-of-range .word offset handling is not implemented for .arch common_v10_v32Overflow in expression, truncated to 16 bitsOverflow in expression, truncated to 8 bitsOverwrite explicitly set Tag_ARC_CPU_basePC not allowed in register listPC part of operand unpredictablePC relative branch to label %s which is not in the instruction spacePC relative relocation not allowed for (internal) type %dPC used as an argument to RPTPC, CT, TR and TT are treated as if they are a single unit but operands must be in different unitsPC-relative access out of rangePC-relative access to misaligned address (%lx)PC-relative access using misaligned offset (%lx)PC-relative access using misaligned symbol (%lx)PC-relative offset not 4-byte-alignedPC-relative offset out of rangePC-relative reference to a different sectionPC-relative relocation must be trivially resolvedPIC code offset overflow (max 16 signed bits)PIC code offset overflow (max 32 signed bits)PIC relocation size does not match operand sizePJ options: -little generate little endian code -big generate big endian code PRU options: -mlink-relax generate relocations for linker relaxation (default). -mno-link-relax don't generate relocations for linker relaxation. PTA operand is a SHcompact symbolPTB operand is a SHmedia symbolParallel opcode cannot contain more than two instructionsParameter named `%s' does not exist for macro `%s'Parameters of an existing subspace can't be modifiedParse failed.Performance extensionPerformance extension 2Perhaps you are missing %%tpoff()?Pipelined instruction: fsrc1 = fdestPlease report this bug. Please use --help to see usage and options for this assembler. Pointless default value for required parameter `%s' in macro `%s'Pointless use of p0 as first operand to .%sPointless use of zero first operand to .prologuePost-decrement mode is not valid for 68HC11.Post-increment mode is not valid for 68HC11.PowerPC options: -a32 generate ELF32/XCOFF32 -a64 generate ELF64/XCOFF64 -u ignored -mpwrx, -mpwr2 generate code for POWER/2 (RIOS2) -mpwr generate code for POWER (RIOS1) -m601 generate code for PowerPC 601 -mppc, -mppc32, -m603, -m604 generate code for PowerPC 603/604 -m403 generate code for PowerPC 403 -m405 generate code for PowerPC 405 -m440 generate code for PowerPC 440 -m464 generate code for PowerPC 464 -m476 generate code for PowerPC 476 -m7400, -m7410, -m7450, -m7455 generate code for PowerPC 7400/7410/7450/7455 -m750cl generate code for PowerPC 750cl -m821, -m850, -m860 generate code for PowerPC 821/850/860 Pre-increment mode is not valid for 68HC11Predicate register expectedPredicate source and target requiredPrefix 'd.' invalid for instruction `%s'Premature end of suffix -- Defaulting to dPrevious .save incompleteProcessor variants are: Prohibited register used for reduced-register, %s.Pseudocode already used %sPseudodirective .file is only valid when generating ELFPseudodirective .loc is only valid when generating ELFQUICKRoT 64-bit extension not applicable to this instructionQUICKRoT extension requires 4 registersQualifying predicate expectedRA register is saved twice.RC/SAE operand must follow immediate operandsRC/SAE operand must precede immediate operandsRDRD, (RI,#offs5)RD,RSRI, #imm4RISC-V options: -fpic generate position-independent code -fno-pic don't generate position-independent code (default) -march=ISA set the RISC-V architecture -mabi=ABI set the RISC-V ABI Radix `%s' unsupported or invalidRd and Rm should be different in mlaRd and Rm should be different in mulRedefining entrynum for sysproc %sRedefining leafproc %sReduced Register configuration (GPR16) optionRedundant `#' suffix operatorsReg not valid for H8/300Register at (r1) can sometimes be corrupted by assembler optimizations. Use .set noat to turn off those optimizations (and this warning).Register must be R0--R7Register must be RnRegister must be address registerRegister must be ivtp or tvtpRegister name %s conflicts with symbol of the same nameRegister name expectedRegister number (R%ld) for double word access must be even.Register number must be EVENRegister number out of range 0..%uRegister symbol %s already defined.Register value annotation ignoredRegisters cannot be used as a prefix of indexed expression [%s]Registers cannot be used within absolute expression [%s]Registers cannot be used within immediate expression [%s]Relaxation should never occurRelaxation to long branches for .arch common_v10_v32 not implementedReloc %d not supported by object file formatRelocatable values require at least WORD storageRelocation %d is not supported by object file format.Relocation %s is not safe for %sRelocation doesn't fit. (relocation value = 0x%lx)Report bugs to %s Reserved word `%s' used as parameter in macro `%s'Rn must not overlap other operandsRotating register index must be a non-negative constantS+core co-processor register expectedS+core register expectedS+core special-register expectedSH options: --little generate little endian code --big generate big endian code --relax alter jump instructions for long displacements --renesas disable optimization with section symbol for compatibility with Renesas assembler. --small align sections to 4 byte boundaries, not 16 --dsp enable sh-dsp insns, and disable floating-point ISAs. --allow-reg-prefix allow '$' as a register name prefix. --isa=[any use most appropriate isa | dsp same as '-dsp' | fpSHF_ALLOC isn't set for GNU_MBIND section: %sSHmedia code not allowed in same section as constants and SHcompact codeSIMD scalar or floating-point register expectedSMC is not permitted on this architectureSP and PC not permitted in .unwind_movsp directiveSP not allowed in register listSPARC options: SPU options: --apuasm emulate behaviour of apuasm SRS base register must be r13SSE instruction `%s' is usedSVC is not permitted on this architectureSVE predicate register expectedSVE vector register expectedSYMBOL TABLE not implementedS^# may only read-accessS^# needs expressionSame src/dest register is used (`r%d'), result is undefinedSame src/dest register is used (`r%d'),result is undefinedScaled-indexed addressing mode combined with scaled-indexSecond operand of .save contradicts .prologueSecond operand to .%s not a constantSecond operand to .prologue must be a general registerSecond operand to .prologue must be the first of %d general registersSecond operand to .restore must be a constant >= 0Second operand to .save not a valid registerSecond operand to .save.b must be a general registerSecond operand to .save.b must be the first of %d general registersSecond operand to .save.g must be a general registerSecond operand to .save.g must be the first of %d general registersSecond operand to .save.gf must be a non-negative 20-bit constantSecond operand to .unwabi must be a constantSection switching in code is not supported.Semantics error. This type of operand can not be relocated, it must be an assembly-time constantShift value > 32. using Short branches, Undefined, SVC, LDM/STMShort literal overflow(%ld.), immediate mode assumed.Signed immediate value %ld too largeSize of frame exceeds maximum of 96 registersSize of rotating registers exceeds frame sizeSomething forgot to clean up Source and destination register should not be equalSource registers must be in the same unitSpurious `,' or bad indirect register addressing mode.Spurious operands; (%d operands/instruction max)Standalone `#' is illegalString extensionSubstitution symbols must begin with a letterSubtype %d is not recognized.Sunplus-v2-0-0-20060510 Support for 64-bit arithmetic not compiled in.Supported ARCH values are:Swapping instruction orderSymbol %s used as immediate operand in PIC mode.Symbol '%s' could not be created.Symbol `%s' can not be both weak and commonSymbol expectedSymbol missing Symbol missing for .set/.equSymbol used as immediate for mbar instructionSymbol used as immediate for shift instructionSymbol used as immediate value for msrset/msrclr instructionsSyntax in scaled-indexed mode, use [Rn:m] where n=[0..7] m={b,w,d,q}TLS relocation against a constantTLS relocation not allowed in FLIX bundleTLS relocation size does not match operand sizeTLS_*_S9 relocs are not supported yetTMS320C6000 options: TOC section size exceeds 64kTOKEN TRACE not implementedTag must come before qualifying predicate.Tag name expectedTags on unwind pseudo-ops aren't supported, yetTarget processor does not support this instruction.The ".%s" pseudo-op is not implemented The %s operand doesn't matchThe .BTEQU pseudo-op is not implemented.The .DEFINE pseudo-op is not implementedThe .ENTER pseudo-op is not supportedThe .LEAVE pseudo-op is not supportedThe .MACRO pseudo-op is not implementedThe 64 bit file format is used without esame instructions.The `.abi %s' directive is not valid with this architectureThe `.mode %s' directive is not valid with this architectureThe debugger will corrupt bt (r25). If you don't need to debug this code use .set nobreak to turn off this warning.The debugger will corrupt sstatus/ba (r30). If you don't need to debug this code use .set nobreak to turn off this warning.The following ARC-specific assembler options are deprecated and are accepted for compatibility only: The option "--no-allow-flix" prohibits multi-slot flix.The trap id must be a constant.This architecture doesn't support atomic instructionThis architecture doesn't support mmuThis assembler does not support processor generation %ldThis assembler was configured for a target of `%s' and default, cpu type `%s'. This assembler was configured for a target of `%s'. This coprocessor register access is deprecated in ARMv8This immediate requires 0 MOD 16 alignmentThis immediate requires 0 MOD 2 alignmentThis immediate requires 0 MOD 4 alignmentThis immediate requires 0 MOD 8 alignmentThis instruction may be unpredictable if executed on M-profile cores with interrupts enabled.This is the location of the conflicting usageThis operand must be constant at assembly timeThis operator only produces two byte values.This program is free software; you may redistribute it under the terms of the GNU General Public License version 3 or later. This program has absolutely no warranty. Thumb does not support NOP with hintsThumb does not support conditional executionThumb does not support negative register indexingThumb does not support register indexing with writebackThumb does not support register post-indexingThumb does not support the 2-argument form of this instructionThumb does not support this addressing modeThumb encoding does not support an immediate hereThumb encoding does not support rotationThumb load/store multiple does not support {reglist}^Thumb supports only LSL in shifted register indexingThumb-2 MUL must not set flagsThumb-2 instruction only valid in unified syntaxThumb2 branch out of rangeToo few operands to '%s'.Too many argument. `%s'Too many instructions for bundle.Too many operandsToo many operands passed to instructionToo many operands scannedToo many operands: %sToo many registers poppedTrap id `%ld' is out of range.Trap id must be within [0x30..0x39] or [0x40..0xff].Treating '%-*s' as a symbol.Tried to .set unrecognized mode `%s'Tried to convert PC relative branch to absolute jumpTrying to 'bal' to %sTwo IU instructions may not be executed in parallelTwo MU instructions may not be executed in parallelTwo instructions in the same bundle both write to register %s, which is not allowed.Unable to allocate memory for new instructions Unable to determine default target processor from string: %sUnable to find %s relocation for instruction %sUnable to generate `%s' compliant code without mthc1Unable to mix instructions as specifiedUnable to parse TLS base: %sUnable to process relocation for thumb opcode: %lxUnable to produce reloc against symbol '%s'Unable to use @pcl relocation for insn %sUnable to use @plt relocation for insn %sUnaligned operand. Needs to be 16bit alignedUnaligned operand. Needs to be 32bit alignedUnary operator %c ignored because bad operand followsUnbalanced parenthesis in %s operand.Unbalanced parenthesis in operand %dUndefined .EXPORT/.IMPORT argument (ignored): %sUndefined absolute constant: '%s'.Undefined register: '%s'.Undefined space: '%s' Assuming space number = 0.Undefined substitution symbol '%s'Unexpected branch conversion with `%x'Unexpected character '%c' after operand %d to %s.Unexpected reference to a symbol in a non-code sectionUnexpected return value [%d] from parse_toc_entry! Unhandled dependency %s for %s (%s), note %dUnhandled reloc typeUnimplemented register `%s' specifiedUnknown .syntax operandUnknown CPU identifier `%s'Unknown TMS320C30 instruction: %sUnknown cpu -mcpu=%sUnknown exception: `%s'Unknown extensionUnknown indirect addressing modeUnknown instruction '%s'Unknown opcode `%.*s'.Unknown opcode `%s'Unknown opcode `%s'.Unknown opcode: `%s'Unknown operatorUnknown processor register (32 bit) : `%d'Unknown processor register : `%d'Unknown psr option `%s'Unknown register pair - index relative mode: `%d'Unknown register pair: `%d'Unknown register: `%d'Unknown reloc in md_apply_fix: %sUnknown relocation encountered in md_apply_fix.Unknown relocation operand: !%sUnknown relocation operand: @%sUnknown segment typeUnknown size of floating point registersUnknown temporary pseudo registerUnknown typeUnknown type %c Unknown/unsupported address literal typeUnmatched high relocationUnmatched high/shigh relocUnrecognised CPU errata name starting here: %sUnrecognised option: -hiddenUnrecognized .LEVEL argument Unrecognized .option directive: %s Unrecognized .type argumentUnrecognized condition code "%s"Unrecognized dependency specifier %d Unrecognized field type '%c'Unrecognized fix-up (0x%08lx)Unrecognized indirect address format "%s"Unrecognized instruction "%s"Unrecognized opcode format: `%s'Unrecognized opcode, %s.Unrecognized opcode: `%s'Unrecognized operand list '%s' for instruction '%s'Unrecognized operand/register, %s.Unrecognized option '-x%s'Unrecognized option following -KUnrecognized or unsupported floating point constantUnrecognized parallel instruction "%s"Unrecognized parallel instruction '%s'Unrecognized parallel instruction combination "%s || %s"Unrecognized predicate relation typeUnrecognized section '%s'Unrecognized status bit "%s"Unrecognized struct/union tag '%s'Unrecognized substitution symbol functionUnrecognized version '%s'Unsigned immediate value %ld too largeUnsupported RISC-V relocation number %dUnsupported broadcast: `%s'Unsupported fixup size %dUnsupported instruction set extension: %sUnsupported operation on relocUnsupported processor generation %dUnsupported relocation size %dUnsupported use of %sUnsupported use of .gpwordUnsupported use of spUnterminated string after absolute expressionUnwind directive not followed by an instruction.Usage: %s [option...] [asmfile...] Use of .def/.ref is deprecated. Use .global insteadUse of PC here is UNPREDICTABLEUse of PC here is deprecatedUse of an RX string instruction detected in a file being assembled without string instruction supportUse of p0 is not valid in this contextUse of r%u as a source register is deprecated when r%u is the destination register.Use the .mmregs directive to use memory-mapped register names such as '%s'Used $at without ".set noat"Used FPU instructions requires enabling FPU extensionUsed more than the available 48 rotating registersUsed more than the available 96 rotating registersUsed more than the declared %d rotating registersUsing ENTRY rather than CODE in export directive for %sUsing a constant as second operand to .prologue is deprecatedUsing old style, %%hi(expr), please change to PPC style, expr@h.Using old style, %%lo(expr), please change to PPC style, expr@l.Using temp register (r1)Using temp register(r1)VAX options: -d LENGTH ignored -J ignored -S ignored -t FILE ignored -T ignored -V ignored VFP registers must be adjacentVFP single or double precision register expectedVFP single precision register expectedVFP single, double or Neon quad precision register expectedVFP system register expectedVFP/Neon double precision register expectedVIP_BEGIN error:%sVLIW packing constraint violationVLIW packing used for -mno-packVMS options: -+ encode (don't truncate) names longer than 64 characters -H show new symbol after hash truncation -replace/-noreplace enable or disable the optimization of procedure calls VMS options: -+ hash encode names longer than 31 characters -1 `const' handling compatible with gcc 1.x -H show new symbol after hash truncation -h NUM don't hash mixed-case names, and adjust case: 0 = upper, 2 = lower, 3 = preserve case -v"VERSION" code being assembled was produced by compiler "VERSION" Value %d doesn't fit in signed %d-bit fieldValue %d doesn't fit in unsigned %d-bit fieldValue %ld not aligned by 2 for 10-bit PC-relative branch.Value %ld not aligned by 2 for 9-bit PC-relative branch.Value %ld too large for 10-bit PC-relative branch.Value %ld too large for 8-bit PC-relative branch.Value %ld too large for 9-bit PC-relative branch.Value for ENTRY_FR must be in the range 12..21 Value for ENTRY_GR must be in the range 3..18 Value for ENTRY_SR must be 3 Value for parameter `%s' of macro `%s' was already specifiedValue not in 16 bit range: %ldValue not in 16 bit signed range: %ldValue not in 4 bit unsigned range: %ldValue not in 5 bit unsigned range: %ldValue not in 6 bit range: %ldValue not in 6 bit unsigned range: %ldValue not in 8 bit range: %ldValue not in 8 bit signed range: %ldValue out of 16-bit range.Value out of 3-bit range.Value out of 4-bit range.Value out of 5-bit range.Value truncated to 62 bitsVariable is accessed using small data read only anchor, but it is not in the small data read only sectionVariable is accessed using small data read write anchor, but it is not in the small data read write sectionVery short instr to option, ie you can't do it on a NULLstrVirtual memory exhaustedWarning: Warning: conditional outside an IT block for Thumb.Warning: duplicated register (r%d) in register listWarning: internal error: forgetting to set endndx of %sWarning: register range not in ascending orderWrites to register '%s' are not allowed.Wrong displacement %dWrong number of input operandsWrong number of operandsWrong number of output operandsWrong numbers of operands in default, check ns32k-opcodes.hWrong register in floating-point reglistWrong register in register indirect mode.Wrong size pointer register for architecture.XScale accumulator register expectedXtensa absolute literals option not supported; ignored[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s[0-9]H labels do not mix with dot-pseudos[0-9]H labels may not appear alone on a line[PC] index banned[]index same as ()+register: unpredictable[]index same as -()register: unpredictable[no-]generics is deprecated; use [no-]transform instead[no-]relax is deprecated; use [no-]transform instead[tocv] symbol is not a toc symbol`%s %d' after `%s %d' from %s:%u`%s %d' but no chunk open yet`%s%s' can't be used for write mask`%s%s' not allowed with `%s%c'`%s' Illegal count-register combination.`%s' Illegal use of register.`%s' Illegal use of registers.`%s' and `%s' can't be undefined in `%s' - `%s'`%s' can't be equated to common symbol `%s'`%s' can't be undefined in `%s' - `%s' {%s section}`%s' can't be undefined in `%s' {%s section} - `%s'`%s' can't be versioned to common symbol '%s'`%s' can't go in %s of %s template`%s' cannot be predicated`%s' cannot be used here`%s' cannot be used with `%s'`%s' does not fit into %s template`%s' does not fit into bundle`%s' does not support legacy NaN`%s' has undefined result`%s' is already the alias of %s `%s'`%s' is deprecated, use `%s'`%s' is not a valid %s expression`%s' is not a valid parameter qualifier for `%s' in macro `%s'`%s' is not supported in 64-bit mode`%s' is not supported on `%s%s'`%s' is not supported on `%s'`%s' is not valid here (expected `%c%s%s%c')`%s' is only supported in 64-bit mode`%s' must be last in bundle`%s' must be last in instruction group`%s' operand %d must use `%ses' segment`%s' should be an operand to this .endp`%s' symbol without preceding function`%s' was already defined`%s' was already used as parameter (or another local) name`%s' was not defined within procedure`%s' was not specified with previous .proc`&' serial number operator is not supported`)' required`,' required`.abi 32' but command-line options do not specify 32-bit ABI`.abi 64' but command-line options do not specify 64-bit ABI`af' must appear alone`fp=32' used with a 64-bit ABI`fp=32' used with a MIPS R6 cpu`fp=64' used with a 32-bit ABI`fp=64' used with a 32-bit fpu`fp=xx' cannot be used with `singlefloat'`fp=xx' used with a cpu lacking ldc1/sdc1 instructions`gp=32' used with a 64-bit ABI`gp=64' used with a 32-bit ABI`gp=64' used with a 32-bit processor`nooddspreg` cannot be used with a 64-bit ABI`noreorder' must be set before `nomacro'a NOP might be needed before the EINTa NOP might be needed here because of successive changes in interrupt statea bignum with underscores may not have more than 8 hex digits in any worda bignum with underscores must have exactly 4 wordsa destination register must be supplieda different %s was already specified, is now %sa register has no addressa reloc on this operand implies an overflowabsolute sections are not supportedaccumulator not a valid destinationaddend used with $DSBT_INDEXaddress calculation needs a strongly defined nearby symboladdress offset must be half word alignmentaddress offset must be word alignmentaddress prohibits #address prohibits ()address prohibits ()+address prohibits -()address prohibits @address prohibits []address prohibits displacement length specifieraddress prohibits registeraddress too high for vector table jmp/jsraddress units must be one of %saddressing mode not supportedalias = %s align value not recognized, using sizealignment is not a positive numberalignment is not a power of 2alignment must be constantalignment negative, 0 assumedalignment negative; 0 assumedalignment not a power of 2alignment padding (%lu byte) not a multiple of %ldalignment padding (%lu bytes) not a multiple of %ldalignment too large, %d assumedalignment too large: %u assumedalignment too large; %d assumedalignment too large; assuming %dalignment too large; assuming %ldalignments greater than %d bytes not supported in .text sections.already assembled instructionsambiguous flags combination - '.profiler' directive ignored.ambiguous memory operand size for `%s`ambiguous operand size for `%s'an .indirect_symbol must be in a symbol pointer or stub section.architectural extension `%s' is not allowed for the current base architecturearchitectural extensions must be specified in alphabetical orderarchitecture `%s' unrecognizedarchitecture bumped from "%s" to "%s" on "%s"architecture features both enabled and disabledarchitecture of opcode conflicts with that of earlier instruction(s)architecture variant invalidassemble Thumb codeassemble for big-endianassemble for little-endianassembly 0x%08x, expected %sassembly state not set for first frag in section %sassuming %s on symbolassuming all members of group `%s' are COMDATat most %d displacement operands are allowedat most %d immediate operands are allowedattaching copyright header %s: %sattaching version header %s: %sattempt to .org/.space backwards? (%ld)attempt to .space/.bes backwards? (%ld)attempt to add an indirect_symbol to a stub or reference section with a zero-sized element at %sattempt to allocate data in absolute sectionattempt to allocate data in common sectionattempt to branch into different segmentattempt to fill absolute section with non-zero valueattempt to fill section `%s' with non-zero valueattempt to get value of unresolved symbol `%s'attempt to move .org backwardsattempt to re-define symbol `%s'attempt to recreate an unwind entryattempt to redefine `%s' with a different lengthattempt to redefine pseudo-op `%s' ignoredattempt to redefine symbolattempt to redefine typed aliasattempt to store float in absolute sectionattempt to store float in section `%s'attempt to store non-empty string in section `%s'attempt to store non-zero value in section `%s'attempt to store value in absolute sectionattempt to use an ARM instruction on a Thumb-only processor -- `%s'backward ref to unknown label "%d:"bad .common segment %sbad .fmask directivebad .frame directivebad .longcall formatbad .mask directivebad .mask/.fmask directivebad .nan directivebad .relax formatbad .reserve segment -- expected BSS segmentbad .section directive: want a,e,v,w,x,M,S,G,T in stringbad .section directive: want a,l,w,x,M,S,G,T in stringbad .section directive: want a,o,s,w,x,M,S,G,T in stringbad .section directive: want a,s,w,x,M,S,G,T in stringbad .section directive: want a,v,w,x,M,S in stringbad .section directive: want a,w,x,M,S,G,T in stringbad .uses formatbad .weakext directivebad COFF debugging informationbad RVC field specifier 'C%c' bad alignmentbad alignment of %d bytes in literal poolbad argument to %s_check directive.bad argument to syntax directive.bad arguments to instructionbad base register: must be r0bad bitmask specified after APSRbad call to MD_ATOF()bad call to md_atofbad combined pmuls output operandbad coprocessor idbad defsym; format is --defsym name=valuebad element type for instructionbad escaped character in stringbad expressionbad expression syntaxbad floating literal: %sbad floating-point constant: exponent overflowbad floating-point constant: unknown error code=%dbad format for ifc or ifncbad format of OPT NEST=depthbad frag at %p : fix %ld addr %ld %ld bad functional unit for operand %u of '%.*s'bad immediate value for 8-bit offset (%ld)bad immediate value for offset (%ld)bad instruction `%s'bad instruction formatbad instruction syntaxbad list lengthbad list length for table lookupbad list type for instructionbad literal size bad memory operand `%s'bad number of operands to '%.*s'bad offset 0x%08lX (must be an 8-bit number of words)bad offset 0x%08lX (must be word-aligned)bad offset 0x%08lX (only 12 bits available for the magnitude)bad offset 0x%08lX (only 8 bits available for the magnitude)bad opcode or operandsbad operand %u of '%.*s'bad operand combination for '%.*s'bad or irreducible absolute expressionbad or irreducible absolute expression; zero assumedbad or missing co-processor numberbad or unhandled relocation type: 0x%02xbad personality routine numberbad predicate '%s'bad range in register listbad register expressionbad register for mrsbad register for operand %u of '%.*s'bad register for post-indexbad register in []bad register listbad register list: %sbad register name `%s'bad register name: %sbad register number: %sbad register or register pair for operand %u of '%.*s'bad register pair for operand %u of '%.*s'bad register rangebad relaxation statebad reloc expressionbad relocation expression for '%s'bad relocation fixup type (%d)bad segmentbad size %d in type specifierbad size %d in vector width specifierbad starting register: r0 and r15 invalidbad string constantbad symbol suffixbad type for registerbad type for scalarbad type in Neon instructionbad value (%s) for %sbad vector arrangement typebad/missing psr specifierbadly formed .dim directivebadly formed .dim directive ignoredbadly formed .size directivebadly formed .weak directive ignoredbadly formed expression near %sbase and offset must be from the same unitbase register expectedbase register specified but zerobase register written back, and overlaps one of transfer registersbase register written back, and overlaps second transfer registerbase unit must be either A0 or A1base unit must be one of %sbfd-target = %s bfd_set_section_flags: %sbig endian mode is not supportedbignum invalidbignum invalid; zero assumedbignum truncated to %d bytebignum truncated to %d bytesbit-field extends past end of registerblx to '%s' an ARM ISA state function changed to blblx to Thumb func '%s' from Thumb ISA state changed to blboth insns for !gpdisp!%ld must be in the same sectionbr_gr record before region record!br_mem record before region record!bra or bsr with undefined symbol.branch %s is always truebranch address range overflow (0x%lx)branch must be last instruction in IT blockbranch offset %d out of rangebranch offset %d out of range %d to %dbranch offset out of range branch operand has odd offset (%lx) branch out of rangebranch prediction invalid on this opcodebranch relaxation failed branch relaxation is not supported in `%s'branch target frequency must be greater than 0branch target not word alignedbranch to a symbol in another ISA modebranch to misaligned address (0x%lx)branching or jumping to a loop end may trigger hardware erratabreak outside of structured loopbroadcast is needed for operand of such typebroadcast not on source memory operandbroken assembler, no assembly attemptedbyte count constant %ld is out of range [1..%d]byte displacement out of rangebyte or halfword not valid for base registercall target address 0x%08x out of range 0x%08x to 0x%08xcall to md_convert_frag call to md_convert_frag call to md_estimate_size_before_relax call to md_estimate_size_before_relax call to tc_aout_fix_to_chars can not do %d byte pc-relative relocationcan not do %d byte relocationcan not resolve expressioncan only load two consecutive registerscan only store two consecutive registerscan only transfer two consecutive registerscan't []index a register, because it has no addresscan't change index for operandcan't close %s: %scan't close `%s'can't create %s: %scan't create group: %scan't create relocationcan't create section %scan't encode register '%s%s' in an instruction requiring REX prefix.can't extend fragcan't extend frag %lu charcan't extend frag %lu charscan't fill %ld byte in section %s of %s: '%s'can't fill %ld bytes in section %s of %s: '%s'can't find fixup pointed to by .usescan't find opcodecan't find opcode can't find previous opcode can't handle expressioncan't handle generation of literal/labels yetcan't handle non absolute segment in `%s'can't handle undefined OP TYPEcan't hash %s: %scan't have relocation for ipushcan't make global register symbol `%s'can't mix positional and keyword argumentscan't mix relocation modifier with explicit shiftcan't open %s for reading: %scan't open %s: %scan't open `%s' for writingcan't open a bfd on stdout %scan't open macro library file '%s' for reading: %scan't predecrementcan't read from %s: %scan't redefine the index of a scalar aliascan't redefine the type of a register aliascan't redefine type for operandcan't represent relocation type %scan't resolve `%s' {%s section} - `%s' {%s section}can't resolve value for symbol `%s'can't set section flags for section %scan't start writing .mdebug section: %scan't use COBR format with external labelcan't use Neon quad register herecan't use R0 herecan't use alignment with this instructioncan't use high part of register in operand %dcan't use register '%s%s' as operand %d in '%s'.can't write %ld byte to section %s of %s: '%s'can't write %ld bytes to section %s of %s: '%s'cannot assemble DSP instruction, DSP option not set: %scannot assemble FPU instruction, FPU option not set: %scannot assemble into a literal fragmentcannot both predecrement and postincrementcannot branch to odd addresscannot change .bundle_align_mode inside .bundle_lockcannot change section or subsection inside .bundle_lockcannot combine index with optioncannot combine pre- and post-indexingcannot convert expression symbol %s to complex relocationcannot create 64-bit relocationcannot create floating-point numbercannot decode instruction formatcannot define symbol `%s' in absolute sectioncannot determine Thumb instruction size. Use .inst.n/.inst.w insteadcannot do %s %u byte relocationcannot do %u byte pc-relative relocationcannot do %u-byte relocationcannot emit PC relative %s relocation%s%scannot emit relocation %s against subsy symbol %scannot encode misaligned addend in the relocatable field (0x%lx)cannot encode opcode "%s"cannot encode opcode "%s" in the given format "%s"cannot find suitable trampolinecannot generate relocation type for symbol %s, code %scannot honor width suffix -- `%s'cannot make a relative jump to an absolute locationcannot mask instruction using no functional unitcannot override zerofill section type for `%s,%s'cannot pack %s and %s togethercannot pack %s and %s together with a 16-bit insncannot pack %s into slot P1cannot pack %s with a 16-bit insncannot represent %s relocation in object filecannot represent %s relocation in this object file formatcannot represent %s relocation in this object file format1cannot represent `%s' relocation in object filecannot represent relocation type %scannot represent relocation type %s in x32 modecannot resolve @slotcount parametercannot set literal_prefix inside literal fragmentcannot use `%s' in this sectioncannot use indirect addressing with the PCcannot use partial register %s for addressingcannot use post-indexing with PC-relative addressingcannot use post-indexing with this instructioncannot use register index with PC-relative addressingcannot use register index with this instructioncannot use writeback with PC-relative addressingcannot use writeback with this instructioncanonical = %s character constant too largecharacter following name is not '#'cmpu doesn't support condition code %sco-processor offset out of rangeco-processor register expectedcode is ATPCS conformantcode uses 26-bit program countercode uses 32-bit program countercomma expected between operandscomma is expectedcomma missing in .xstabscommon alignment not a power of 2comparison must be with register or #0condition code %s value (%d) too largecondition code invalid for jrcondition code register should be 0 or 4 for %s, was %dcondition code register should be even for %s, was %dcondition not followed by conditionalizable insncondition requiredcondition sa cannot be used hereconditional branch or jal insn's operand references R%ld of previous arithmetic or logic insn.conditional branch out of rangeconditional branch target not word alignedconditional infixes are deprecated in unified syntaxconditional instruction cannot use B flagconditional instruction cannot use G flagconditional instruction cannot use R flagconflicting ISA extension attributes.confusing relocation expressionsconfusion in formal parametersconstant doesn't fit in 4 bitsconstant expression expectedconstant expression or register list expectedconstant expression requiredconstant expression required.constant generator destination register found in %sconstant generator source register found in %sconstant offset requiredconstant out of 8-bit range: %dconstant shift amount requiredconstant too big to fit into instructionconstant value requiredcontrol register '%s' not supported on this architecturecontrol register expected, but saw '%.6s'convert_frag core and copro insn lengths must total 32 bits.core and copro insn lengths must total 64 bits.core register %s value (%d) too largecould not assemble: %scould not build transition for %s => %scould not parse INSN_PATTERN '%s'could not parse INSN_REPL '%s'could not parse template definitioncould not set architecture and machinecould not skip to %ld in file `%s'could not update architecture and machinecould not write .mdebug section: %scouldn't find a valid instruction formatcouldn't find relocation to usecpu `%s' unrecognizedcpu-type = %s cpu4: not converting PUSH #4 to shorter formcpu4: not converting PUSH #8 to shorter formcr%ld is a reserved control registerctoff() is not supported by the rh850 ABI. Use -mgcc-abi insteadctoff() relocation used on an instruction which does not support itcustom instruction opcode %u out of range %u to %ud0/d1 registersdangerous MULS/MULU location; give it higher alignmentdangling `__gcc_isr %d'dangling `__gcc_isr'data dependency: %s %s -- %s %s (%d/%d bubble)data in executable sectiondata item with alignment larger than locationdata transfer register cannot be halfworddefault mask isn't alloweddest and source1 must be the same registerdest must overlap one source registerdestinationdestination for add/subtract can only be R2 or R3destination for multiply can only be R0 or R1destination operand must be 16 bit registerdestination operand must be 16bit absolute addressdestination operand must be 8 bit registerdestination register is same for parallel insnsdestination register modified by displacement-post-modified addressdestination register must be full-worddestination register must be r1destination register same as write-back basedestination register should be even numbereddestination unit must be RDdetected global register use not covered by .register pseudo-opdifference of two symbols only supported with .long, .short, or .bytedirective %s cannot be negateddirective .big encountered when option -big requireddirective .little encountered when option -little requireddirective LOC from within a BSPEC/ESPEC pair is not supporteddirective LOCAL must be placed in code or datadirectives are not valid inside bundlesdisable warnings about symobls that match instructionsdiscriminator less than zerodisplacement is too largedisplacement must be an unsigned 8-bit numberdisplacement overflows 12-bit fielddisplacement overflows 8-bit fielddisplacement to defined symbol %s overflows 12-bit fielddisplacement to defined symbol %s overflows 8-bit fielddisplacement to undefined symbol %s overflows 12-bit fielddisplacement to undefined symbol %s overflows 8-bit field displacement too large (%d)displacement too large for this architecture; needs 68020 or higherdiv / mul are reserved instructionsdivide by zerodivision by zerodivision by zero when setting `%s'dla used to load 32-bit register; recommend using la insteaddo not output verbose error messagesdo not warn on use of deprecated featuredoes not match begin %s%s at %s:%ddon't use Rn-Rm syntax with non-unit stridedropping register %d in section %s does not match using register %ddropping register %d in section %s previously used in section %sdsp immediate shift value not constantduplicate !tlsgd!%ldduplicate !tlsldm!%ldduplicate ".else"duplicate .fnstart directiveduplicate .handlerdata directiveduplicate .personality directiveduplicate .personalityindex directiveduplicate datalabel operator ignoredduplicate instruction %sduplicate macro %sduplicated `%s'duplicated psr bit specifierelements must be smaller than reversal regionelse without matching ifemit_one_bundle: unexpected dynamic opempty label field for ISempty symbol name in .def; ignoredempty vector register listemulations not handled in this configurationend of file after a one-character quote; \0 insertedend of file in commentend of file in comment; newline insertedend of file in escape characterend of file in multiline commentend of file in string; '%c' insertedend of file inside conditionalend of file not at end of a line; newline insertedend of macro inside conditionalend of vector register list not foundend on line errorendf without forendi without matching ifending register must be r15endw without whileentity size for SHF_MERGE not specifiedentry instruction with stack decrement < 16error checking for overflow - broken assemblererror constructing %s pseudo-op table: %serror parsing element/structure listerror setting flags for "%s": %serror setting flags for ".sbss": %serror: unsupported #foo() directive used on symbolestimate size estimate_size_before_relax calledeven register number requiredeven register requiredexcess operands to %sexcess operands: '%s'expected #constantexpected #n as first argument of %sexpected %cexpected ',' after section nameexpected ',' after symbol nameexpected ',' after symbol sizeexpected ']', not %c in %sexpected , expected .L, .W or .B for register in indexed addressing modeexpected 0 operands for generated labelexpected 0 or 1expected or or operandexpected expected , expected , expected , expected @(exp, reg16)expected EP registerexpected `%s' to have already been set for .vtable_inheritexpected a %s name followed by a `,'expected address expressionexpected alignment after sizeexpected closing parenexpected commaexpected comma after "%s"expected comma after instruction nameexpected comma after major opcodeexpected comma after nameexpected comma after name "%s"expected comma after name `%s' in .localentry directiveexpected comma after name `%s' in .size directiveexpected comma after name in .symverexpected comma after name in .vtable_entryexpected comma after name in .vtable_inheritexpected comma after register modeexpected comma after register numberexpected comma after symbol nameexpected comma after symbol-name: rest of line ignored.expected comma or colon after symbol name; rest of line ignoredexpected comma separatorexpected constant expression as first argument of %sexpected constant expression, got %sexpected constant in the range 2..16expected constant or register name as argument to RPT insnexpected constant value as argument to RPTexpected expressionexpected expression, got %sexpected fill pattern missingexpected first argument of %s to be in the range 1-4expected indexexpected numeric constantexpected one operand for generated literalexpected quoted stringexpected registerexpected register as second argument of %sexpected register listexpected register name or constant as first argument of %sexpected simple numberexpected symbolexpected symbol nameexpected valid addressing mode for mova: "@(disp, ea.sz),ERn"expected value of first argument of %s to fit into 20-bitsexpected }expecting %c near %sexpecting )expecting ]expecting `)' after scale factor in `%s'expecting `,' or `)' after base register in `%s'expecting `,' or `)' after index register in `%s'expecting a register for operand %dexpecting comma delimited operandsexpecting comma delimited register operandsexpecting control registerexpecting either ON or OFF after .listexpecting index register or scale factor after `,'; got '%c'expecting indirect branch instruction after `notrack'expecting indirect register `($rA)'expecting indirect register `($rX)'expecting lockable instruction after `lock'expecting mnemonic; got nothingexpecting opcode string in self test modeexpecting operand after ','; got nothingexpecting operand before ','; got nothingexpecting prefix; got nothingexpecting registerexpecting scale factor of 1, 2, 4, or 8: got `%s'expecting valid branch instruction after `bnd'expecting {expression doesn't fit in BYTEexpression doesn't fit in WORDexpression errorexpression must be constantexpression not a constantexpression out of range: defaulting to 0expression out of range: defaulting to 1expression syntax errorexpression too complexextended instruction in a branch delay slotextended instruction in delay slotextended operand requested but not requiredextending shift is not permittedextension `%s' unrecognizedextension does not apply to the base architectureextra .LABEL arguments ignored.extra characters '%s' at end of constant expression '%s'extra characters '%s' at end of immediate expression '%s'extra characters '%s' at end of operand '%s'extra characters '%s' at the end of absolute operand '%s'extra closing braceextra colonextra commaextra dotextra opening braceextra stuff on line ignoredextraneous characters at end of numeric section typeextraneous shift as part of operand to shift insnfailed for %d failed general register sanity check.failed regnum sanity check.failed sanity checkfailed sanity check.failed sanity check: long_jumpfailed sanity check: short_jumpfailed special case insn sanity checkfailed to assemble instruction: "%s"failed to parse flagsfailed to read instruction table %s failed to set flags for "%s": %sfailed to set subsections by symbolsfailed to set up debugging information: %sfake .file after real onefall through frequency must be greater than 0field fx_size too small to hold %dfield size must be 16 when value is relocatablefield value "%s" too complex for a bitfieldfield value truncatedfield width "%s" too complex for a bitfieldfield width %lu too big to fit in %d byte: truncated to %d bitsfield width %lu too big to fit in %d bytes: truncated to %d bitsfifthfile finished with an open IT block.file not found: %sfile number %ld already allocatedfile number less than onefilename goes over one page boundaryfill pattern too long, truncating to %ufirstfirst and second operands shall be the same registerfirst operand is floating pointfirst operand is too large for 16-bit signed intfirst operand is too large for a 24-bit displacementfirst register must be r4first transfer register must be evenfixes not all moved from %sflag for {c}psr instruction expectedfloat register should be even, was %dfloating point args are in fp regsfloating point constant too largefloating point number invalidfloating point number invalid; zero assumedfloating point numbers are not implementedfloating-point expression requiredformat = %s format names only valid inside bundlesfound %d operand for '%s': Expected %dfound %d operands for '%s': Expected %dfound '%c', expected: '%c'fourthfr_mem record before region record!fr_var %lu < length %dfr_var (%ld) < length (%d)fraction bits value out of rangeframe reg expected, using $%d.frame size specified twicefrgr_mem record before region record!functional unit already maskedfunctional unit already masked for operand %u of '%.*s'functional unit already used in this execute packetgarbage after index spec ignoredgarbage at end of linegarbage following instructiongenerate PIC codeget_expanded_loop_offset: invalid opcodegr_gr record before region record!gr_mem record before region record!group name for SHF_GROUP not specifiedgroup section `%s' has no group signaturehandlerdata in cantunwind framehard-float conflicts with specified fpuhardware dividehaving the base register in the register list when using write back is UNPREDICTABLEhere is the "else" of the unterminated conditionalhere is the previous ".else"here is the previous ".if"here is the start of the unterminated conditionalhi() relocation used on an instruction which does not support ithi0() relocation used on an instruction which does not support ithigh bits set in register list expressionhint in B unit can't be usedhint in B unit may be treated as nophint.b may be treated as nophint.b shouldn't be usediWMMXt control register expectediWMMXt data or control register expectediWMMXt data register expectediWMMXt scalar register expectedia64.md_begin: can't hash `%s': %sidentifier+constant@%s means identifier@%s+constantidentifier+constant@got means identifier@got+constantif writeback register is in list, it must be the lowest reg in the listignoring attempt to re-define symbol `%s'.ignoring attempt to redefine built-in register '%s'ignoring attempt to redefine symbol %signoring attempt to undefine built-in register '%s'ignoring attempt to use .unreq on fixed register name: '%s'ignoring bad alignmentignoring changed section attributes for %signoring changed section entity size for %signoring changed section type for %signoring extra '-rename-section' delimiter ':'ignoring fill value in absolute sectionignoring fill value in section `%s'ignoring incorrect section type for %signoring invalid '-rename-section' specification: '%s'ignoring macro exit outside a macro definition.ignoring operands: %s ignoring redefinition of register alias '%s'ignoring unrecognized .endian type `%s'iif convert internal pcrel/binaryiif convert internal pcrel/pointerillegal %s relocation size: %dillegal .stab%c directive, bad characterillegal .stabx expression; zero assumedillegal double indirectionillegal expressionillegal immediate register operand %sillegal indirect referenceillegal literalillegal opcode %s for mcu %sillegal operandillegal operand - register name found where none expectedillegal operandsillegal range of target hardware versionsillegal register after @illegal register after @-illegal register included in listillegal register numberillegal resource usage in bundleillegal use of control registerillegal use of coprocessor registerimm3imm5 should >= 2immediate 0 cannot be used hereimmediate 1 or 2 expectedimmediate cannot be moved by a single instructionimmediate expression requires a # prefiximmediate has bits set outside the operand sizeimmediate is not a power of twoimmediate must be 1 or 2immediate offset not 2-byte-alignedimmediate offset not 4-byte-alignedimmediate offset out of rangeimmediate operand illegal with absolute jumpimmediate operand is not matchimmediate operand is too largeimmediate operand requiredimmediate operand requires iWMMXt2immediate operands sum to greater than 32immediate out of rangeimmediate out of range for insertimmediate out of range for narrowing operationimmediate out of range for shiftimmediate valueimmediate value %d out of range %d to %dimmediate value %llu out of range %u to %luimmediate value %u out of range %u to %uimmediate value 0x%x truncated to 0x%ximmediate value is out of rangeimmediate value must be a multiple of %d at operand %d -- `%s'immediate value not allowed when source & dest differimmediate value out of rangeimmediate value out of range immediate value out of range, expected range [0, 16]immediate value out of range, expected range [1, 32]immediate zero expectedimproper number of operands. Expecting %d, got %dinappropriate arguments for opcode '%s'inappropriate arguments for opcode `%s'incompatible flag %i in line directiveinconsistent types in Neon instructioninconsistent uses of .cfi_sectionsincorrect condition in IT blockincorrect format for multiply parallel instructionincorrect number of operands given in the first instructionincorrect number of operands given in the second instructionincorrect register `%s%s' used with `%c' suffixincorrect register in reglistincorrect register number, ignoringindex and destination registers should be distinctindex not allowed inside register listindex offset out of rangeindex register overlaps transfer registerindex register specified but zeroindex value too big for %sindexed vector register expectedindirect %s without `*'inserting "%s" into %s alias hash table failed: %sinserting "%s" into %s name hash table failed: %sinserting "%s" into string hash table: %sinserting "%s" into symbol table failed: %sinserting "%s" into tag hash table: %sinserting a NOP before EINTinsn can't be combined with parallel processing insninsn cannot be combined with non-nopxinsn cannot be combined with non-nopyinsn cannot be combined with pmulsinstruction %s may not follow another I/O instruction.instruction %s may not follow another memory access instruction.instruction %s requires %d operandinstruction %s requires %d operandsinstruction %s requires MSP430X mcuinstruction %s requires enabling AUDIO extensioninstruction %s requires enabling DIV & DX_REGS extensioninstruction %s requires enabling DX_REGS extensioninstruction %s requires enabling FPU extensioninstruction %s requires enabling FPU_DP extensioninstruction %s requires enabling FPU_MAC extensioninstruction %s requires enabling FPU_SP extensioninstruction %s requires enabling STRING extensioninstruction %s requires enabling performance extensioninstruction %s requires enabling performance extension IIinstruction %s.a does not existinstruction %s: result is always falseinstruction %s: result is always trueinstruction '%.*s' cannot be predicatedinstruction '%s' cannot be executed in parallel.instruction '%s' is for the M32R2 onlyinstruction '%s' is for the M32RX onlyinstruction `%s' after `xacquire' not allowedinstruction `%s' isn't supported in 16-bit mode.instruction address is not a multiple of 16instruction address is not a multiple of 2instruction address is not a multiple of 4instruction address is not a multiple of 8instruction cannot be conditionalinstruction cannot operate on pair valuesinstruction does not accept preindexed addressinginstruction does not accept scaled register indexinstruction does not accept this addressing modeinstruction does not accept unindexed addressinginstruction does not allow shifted indexinstruction does not support unindexed addressinginstruction does not support writebackinstruction does not take a block typeinstruction form not available on this architecture.instruction implicitly accesses R31 of previous load.instruction is always unconditionalinstruction mnemonic too long: %sinstruction not allowed in IT blockinstruction not supported in Thumb16 modeinstruction requires labelinstruction requires label or value in range -511:512instruction requires label sans '$'instruction requires register indexinstruction sequence (write a0, branch, retw) may trigger hardware erratainstructions write to the same destination register.integer 32-bit register expectedinteger 64-bit register expectedinteger operand out of rangeinteger or SP register expectedinteger or zero register expectedinteger register expectedinteger register expected in the extended/shifted operand registerinteger, zero or SP register expectedinternal confusion: relocation in a section without contentsinternal error in argument parsinginternal error: [%s] unexpected code [%lx] in frob symbolinternal error: bad CFA value #%dinternal error: bad argument type %cinternal error: bad file property ID %dinternal error: bad microMIPS opcode (incorrect length: %u): %s %sinternal error: bad microMIPS opcode (opcode/length mismatch): %s %sinternal error: bad relocation #%dinternal error: base section index out of rangeinternal error: broken opcode descriptor for `%s %s' internal error: can't export reloc type %d (`%s')internal error: can't hash `%s': %sinternal error: can't hash `%s': %s internal error: can't hash aux register '%s': %sinternal error: can't hash macro `%s': %sinternal error: can't hash opcode '%s': %sinternal error: can't hash opcode `%s': %sinternal error: can't install fix for reloc type %d (`%s')internal error: failed to allocate %d indirectsymbol pointersinternal error: fixup not contained within fraginternal error: invalid macrointernal error: lookup/get operands failedinternal error: losing opcode: `%s' "%s" internal error: more indirect mach-o symbols than expectedinternal error: reloc %d (`%s') not supported by object file formatinternal error: unknown dwarf2 formatinternal error: unknown nop check stateinternal error: unknown option name '%s'internal error; cannot generate `%s' relocationinternal error? cannot generate `%s' relocationinternal error? cannot generate `%s' relocation (%d, %d)internal failure in parse_register_listinternal inconsistency in %s: bdap.w with no symbolinternal inconsistency in %s: bdapq no symbolinternal inconsistency problem in %s: %lxinternal inconsistency problem in %s: ext. insn %04lxinternal inconsistency problem in %s: fr_subtype %dinternal inconsistency problem in %s: fr_symbol %lxinternal inconsistency problem in %s: insn %04lxinternal inconsistency problem in %s: resolved symbolinternal inconsistency problem: %s called for %d bytesinternal relocation (type: IMMEDIATE) not fixed upinternal: BFD_RELOC_MMIX_BASE_PLUS_OFFSET not resolved to sectioninternal: GREG expression not resolved to sectioninternal: bad RISC-V opcode (bits 0x%lx undefined): %s %sinternal: bad RISC-V opcode (mask error): %s %sinternal: bad RISC-V opcode (unknown operand type `%c'): %s %sinternal: bad RISC-V opcode (unknown operand type `C%c'): %s %sinternal: bad mips opcode (bits 0x%08lx defined): %s %sinternal: bad mips opcode (bits 0x%08lx doubly defined): %s %sinternal: bad mips opcode (bits 0x%08lx undefined): %s %sinternal: bad mips opcode (mask error): %s %sinternal: can't hash `%s': %sinternal: mmix_prefix_name but empty prefixinternal: unexpected relax type %d:%dinternal: unhandled label %sinternal: unknown operand type: %s %sinternal_relocation (type: OFFSET_IMM) not fixed upinterrupt vector for trap instruction out of rangeinvalid %s option for %s cpuinvalid -march= option: `%s'invalid -mavxscalar= option: `%s'invalid -mevexlig= option: `%s'invalid -mevexrcig= option: `%s'invalid -mevexwig= option: `%s'invalid -mfence-as-lock-add= option: `%s'invalid -mmnemonic= option: `%s'invalid -momit-lock-prefix= option: `%s'invalid -moperand-check= option: `%s'invalid -mrelax-relocations= option: `%s'invalid -msse-check= option: `%s'invalid -msyntax= option: `%s'invalid -mtune= option: `%s'invalid in --march=: %sinvalid @slotcount valueinvalid BSPEC expressioninvalid FPA immediate expressioninvalid Hi register with immediateinvalid LOC expressioninvalid NaN setting -mnan=%sinvalid PC-relative operandinvalid PIC referenceinvalid VSIB addressinvalid WakeOnStatus %ldinvalid XFR WideBus Address %ldinvalid abi -mabi=%sinvalid accumulator registerinvalid addressinvalid addressing modeinvalid architectural extensioninvalid architecture %sinvalid architecture -A%sinvalid architecture -xarch=%sinvalid architecture -z%sinvalid architecture option -m%s, ignoredinvalid argument '%s' to -fdebug-prefix-mapinvalid attempt to declare external version name as default in symbol `%s'invalid auto-litpool-limit argumentinvalid auto-litpool-limit argument (range is 100-10000)invalid barrier typeinvalid base register for register offsetinvalid branch operandinvalid byte branch offsetinvalid cache operation nameinvalid char %s beginning operand %d `%s'invalid character %s before operand %dinvalid character %s in mnemonicinvalid character %s in operand %dinvalid characters in inputinvalid co-processor operandinvalid conditioninvalid condition code '%s'invalid condition code nameinvalid configuration option '%s' in transition rule '%s'invalid constantinvalid constant (%lx) after fixupinvalid constant table offset %ldinvalid constant: %d bit expression not in range %d..%dinvalid constant: %d bit expression not in range %u..%uinvalid constant: %d is not word align integerinvalid constant: 10 bit expression not in range [-2^9, 2^9-1]invalid constant: 20 bit expression not in range -2^19..2^19-1invalid constant: 25 bit expression not in range [-16777216, 16777215]invalid constant: 32 bit expression not in range [-0x80000000, 0x7fffffff]invalid constant: 32 bit expression not in range [0, 0xffffffff]invalid constant: 32 bit expression not word aligninvalid constant: bit expression not definedinvalid control register nameinvalid default displacement size "%s". Defaulting to %d.invalid destination memory operandinvalid destination registerinvalid destination register listinvalid destination unitinvalid element selectorinvalid element size %d and vector size combination %cinvalid empty loopinvalid expression evaluation type %dinvalid expression for operand %i of '%s'invalid expression in load/store multipleinvalid expression in operandinvalid expression in the addressinvalid flag '%s'invalid floating point register pair. Valid fp register pair operands are 0, 1, 4, 5, 8, 9, 12 or 13.invalid floating-point constantinvalid fourth registerinvalid frame sizeinvalid hvc expressioninvalid identifier for ".ifdef"invalid immediateinvalid immediate field positioninvalid immediate for address calculation (value = 0x%08lX)invalid immediate for stack address calculationinvalid immediate sizeinvalid immediate valueinvalid immediate: %ld is out of rangeinvalid index registerinvalid index size for coldfireinvalid indirect register sizeinvalid instruction `%s' after `%s'invalid instruction for this architecture; needs invalid instruction shapeinvalid instruction size selected (%d)invalid instruction suffixinvalid last instruction for a zero-overhead loopinvalid length field specifiedinvalid length for .scomm directiveinvalid listing option `%c'invalid literal constant: pool needs to be closerinvalid lrlive '%lu'invalid machine `%s'invalid machine mode `%s'invalid memory operandinvalid merge entity sizeinvalid modeinvalid movx address registerinvalid movx dsp registerinvalid movy address registerinvalid movy dsp registerinvalid neon suffix for non neon instructioninvalid numberinvalid number of registers in the list; %d registers are expected at operand %d -- `%s'invalid number of registers in the list; only 1 register is expected at operand %d -- `%s'invalid offset expressioninvalid offset, target not word aligned (0x%08lX)invalid offset, value too big (0x%08lX)invalid opcodeinvalid opcode '%s' in transition rule '%s'invalid opcode, "%s".invalid operandinvalid operand (%s section) for `%s'invalid operand (%s section) for `%s' when setting `%s'invalid operand in ldminvalid operand in stminvalid operand mode for this architecture; needs 68020 or higherinvalid operand of ()+invalid operand of -()invalid operand of S^#invalid operand size requestedinvalid operand suffixinvalid operand to .code directive (%d) (expecting 16 or 32)invalid operand to opcode %s: `%s'invalid operand, not a 10-bit signed value: %dinvalid operand, not a 11-bit signed value: %dinvalid operand, not a 12-bit signed value: %dinvalid operand, not a 13-bit signed value: %dinvalid operand, not a 16-bit signed value: %dinvalid operand, not a 16-bit unsigned value: %dinvalid operand, not a 5-bit unsigned value: %dinvalid operand, not a 6-bit signed value: %dinvalid operand, not a 6-bit unsigned value: %dinvalid operand, not a multiple of 32: %dinvalid operand, not a multiple of 4: %dinvalid operand, not a multiple of 8: %dinvalid operand, not an even value: %dinvalid operand: expression in PT targetinvalid operandsinvalid operands (%s and %s sections) for `%s'invalid operands (%s and %s sections) for `%s' when setting `%s'invalid operands for cross-unit opinvalid operands for opcodeinvalid operands to %sinvalid operands to opcode %s: `%s'invalid or unsupported encoding in .cfi_lsdainvalid or unsupported encoding in .cfi_personalityinvalid pc-relative addressinvalid performance registerinvalid pref operation nameinvalid priority '%lu'invalid pseudo operationinvalid quickrot register specifiedinvalid quickrot unit specifiedinvalid range in vector register listinvalid registerinvalid register %sinvalid register '%s' for '%s' instructioninvalid register expressioninvalid register for memory accessinvalid register listinvalid register list to push/pop instructioninvalid register maskinvalid register nameinvalid register number (%ld) for '%s'invalid register number (%ld) for '%s' instructioninvalid register number: %d is not in [r0--r7]invalid register operandinvalid register operand #1invalid register operand #2invalid register operand #3invalid register operand #4invalid register operand: %sinvalid register rangeinvalid register type %dinvalid register: r15 illegalinvalid relaxation fragment resultinvalid reloc expressioninvalid relocationinvalid relocation %s for fieldinvalid relocation expressioninvalid relocation for '%s' instructioninvalid relocation for fieldinvalid relocation for instructioninvalid relocation for operand %d of '%s'invalid relocation for operand %i of '%s'invalid relocation in instruction slot %iinvalid rotationinvalid rounding modeinvalid scalar register in listinvalid scale factorinvalid segment "%s"invalid shiftinvalid shift for the register offset addressing modeinvalid shift operatorinvalid shift value: %ldinvalid short form floating point immediate operandinvalid smc expressioninvalid source memory operandinvalid source registerinvalid source register listinvalid source unitinvalid suffixinvalid suffix after register.invalid swi expressioninvalid switch -m%sinvalid symbolic operandinvalid syntax for .dn directiveinvalid syntax for .qn directiveinvalid syntax for .req directiveinvalid syntax for .unreq directiveinvalid system register nameinvalid target hardware versioninvalid type for literal poolinvalid unextended operand valueinvalid unwind opcodeinvalid use of "=immediate"invalid use of %s relocationinvalid use of 'MSL'invalid use of 'MUL'invalid use of 32-bit register offsetinvalid use of 64-bit register offsetinvalid use of operator "%s"invalid use of vector registerinvalid value for special purpose registerinvalid vector register in listinvalid vector register nameinvalid write mask `%s'invalid zeroing-masking `%s'is_stmt value not 0 or 1isa number less than zerojump not 3..10 bytes away (is %d)jump target out of rangejump target out of range; no usable trampoline foundjump to a symbol in another ISA modejump to misaligned address (0x%lx)junk `%s' after expressionjunk `%s' after registerjunk after operand %u of '%.*s'junk at end of line, first unrecognized character is `%c'junk at end of line, first unrecognized character valued 0x%xjunk at end of line: "%s"junk at end of line: `%s'junk at end of machine string, first unrecognized character is `%c'junk found after instruction: %s.%sla must use with symbol. '%s'la used to load 64-bit address; recommend using dla insteadlabel "$%d" redefinedlabel "%d$" redefinedlabel %s was not defined in this dwarf sectionlabel after '||'label after predicatelabel not at start of execute packetlabels are not valid inside bundleslacking labellacking label last register must be r7ldr to register 15 must be 4-byte alignedldrd/strd requires even:odd register pairleb128 operand is an undefined symbol: %sleft operand is a bignum; integer 0 assumedleft operand is a float; integer 0 assumedlength not neededlength of .comm "%s" is already %ld. Not changed to %ld.length of .lcomm "%s" is already %ld. Not changed to %ld.li rd label isn't correct instruction formline %d: rep or repi must include at least 4 instructionsline %d: unable to place address of symbol '%s' into a byteline %d: unable to place address of symbol '%s' into a quadline %d: unable to place address of symbol '%s' into a shortline %d: unable to place value %lx into a byteline %d: unable to place value %lx into a shortline %d: unknown relocation type: 0x%xline number (%d) for .stab%c directive cannot fit in index field (20 bits)line numbers must be positive; line number %d rejectedlink register must be in a low numbered registerlink register unit must be one of %sliteral pool insertion failedliteral pool location required for text-section-literals; specify with .literal_positionliteral pool overflowliteral referenced across section boundarylk addressing modes are invalid for memory-mapped register addressinglmi pseudo instruction should not use a label in imm fieldlo register requiredlo() relocation used on an instruction which does not support itloading the same register in parallel operationlocal label `%s' is not definedlong jump requiredloop containing less than three instructions may trigger hardware errataloop count constant %ld is out of range [1..%d]loop end too close to another loop end may trigger hardware errataloop target does not follow loop instruction in sectionloop too long for LOOP instructionloop: 32-bit displacement not supportedlow register (r0-r15) expected, not '%.100s'lower 16 bits of mask ignoredlui expression not in range 0..1048575m68k and cf features both selectedmacro %s not implemented yetmacro instruction expanded into a wrong size instruction in a 16-bit branch delay slotmacro instruction expanded into a wrong size instruction in a 32-bit branch delay slotmacro instruction expanded into multiple instructionsmacro instruction expanded into multiple instructions in a branch delay slotmacro requires $at register while noat in effectmacro requires $at while $at in usemacro used $at after ".set noat"macros nested too deeplymajor opcode is not sorted for %smajor opcode not in range [0x%02x - 0x%02x]malformed reglist in push/popmask not on destination operandmask trims opcode bits for %smask, index, and destination registers must be distinctmask, index, and destination registers should be distinctmatching operands to opcodemd_apply_fix: unknown r_type 0x%x md_estimate_size_before_relax memory destination needed for instruction `%s' after `xrelease'minor opcode not in range [0x00 - 0x3f]misaligned branch destinationmisaligned datamisaligned offsetmismatch between opcode size and operand sizemismatch between register and suffixmismatch for format '%s': #slots = %d, #opcodes = %dmismatched .ebmismatched element/structure types in listmismatched parenthesesmisplaced .procendmisplaced PIC operandmissing '%c'missing ')'missing ']'missing +missing .endmissing .end at end of assemblymissing .end or .bend at end of filemissing .endp before .cfi_startprocmissing .fnstart before unwinding directivemissing .funcmissing .procmissing =missing CPS flagsmissing DSP name `%s'missing [missing ]missing `)'missing `)' after formals in macro definition `%s'missing `.end'missing `]'missing `lock' with `%s'missing `}'missing `}' in `%s'missing abi name `%s'missing alignmentmissing alignment hintmissing architectural extensionmissing architecture name `%s'missing argumentmissing argument for %s_check directivemissing argument separator ',' for .cpsetupmissing block typemissing break countmissing call argumentmissing call signaturemissing classmissing close quote; (assumed)missing closing '"'missing closing `%c'missing closing bracemissing closing parenthesismissing commamissing comma after insn constant missing comma or colonmissing condition code in structured control directivemissing cpu architecturemissing cpu name `%s'missing domissing element sizemissing emulation mode namemissing end-quotemissing expressionmissing expression in .abiversion directivemissing expression in .localentry directivemissing expression in .size directivemissing flags: one of 'P', 'N' or 'Z' requiredmissing fpu name `%s'missing frame sizemissing immediate expressionmissing labelmissing local expressionmissing local indexmissing model parametermissing namemissing offsetmissing offset in the pre-indexed addressmissing opcodemissing operandmissing operand after commamissing operand; zero assumedmissing or bad offset expressionmissing or invalid displacement expression `%s'missing or invalid displacement expression `%s' taken as 0missing or invalid expression `%s'missing or invalid immediate expression `%s'missing predication typemissing real symbol namemissing reloc typemissing rename stringmissing reserved current_memory/grow_memory argumentmissing rotation field after commamissing separatormissing shift amountmissing sizemissing size expressionmissing sizeof_stub expressionmissing stringmissing symbol namemissing table indexmissing thenmissing to or downtomissing typemissing type suffixmissing valuemissing version name in `%s' for symbol `%s'more than 65K literal poolsmov cannot use RD port as destinationmultiple '||' on same linemultiple branches or jumps in the same bundlemultiple condition specificationsmultiple emulation names specifiedmultiple formats specified for one bundle; using '%s'multiple literals in expansionmultiple movx specificationsmultiple movy specificationsmultiple parallel processing specificationsmultiple predicates on same linemultiple sections remapped to output section %smultiple versions [`%s'|`%s'] for symbol `%s'multiple writes to the same registermust be @(r0,...)must specify extensions to add before specifying those to removeneed PIC qualifier with symbol.need PIC qualifier with symbol. '%s'needs @GOT or @GOTOFF. %snegative alignmentnegative count for %s - ignorednegative offsetnegative sizenegative value ignored in %sneither Power nor PowerPC opcodes were selected.nested .bs blocksnested .ent directivesnested software pipelined loopnew line in titlenew section '%s' defined without attributes - this might cause problemsnext outside of structured loopno %d-byte relocations availableno '(' to match ')'no '[' to match ']'no .cprestore pseudo-op used in PIC codeno .frame pseudo-op used in PIC codeno architecture contains all the instructions used no compiled in support for 32bit x86_64no compiled in support for 64 bit object file formatno compiled in support for x86_64no current file pointerno entry symbol for global function '%s'no file name following -t optionno filename following .INCLUDE pseudo-opno floating point unit specifiedno function type on PLT relocno hppa_fixup entry for fixup type 0x%xno instruction mnemonic suffix given and no register operands; can't size instructionno instruction mnemonic suffix given; can't determine immediate sizeno known dwarf XCOFF section for flag 0x%08x no previous section to return to, ignored.no registered fragment for literalno relaxation found for this instruction.no sequence number after !%sno size modifier after period, .w assumedno such architecture modifier: `%s'no such architecture: `%s'no such instruction: `%s'no such machine extension `%s'no such sfr in this architectureno suitable GREG definition for operandsno tag specified for %sno way to handle .file within .ent/.end sectionno-auto-litpools is incompatible with auto-litpool-limitnon-PIC jump used in PIC librarynon-absolute expression in constant fieldnon-absolute value used with .space/.besnon-constant .%cleb128 is not supportednon-constant byte countnon-constant expression in ".elseif" statementnon-constant expression in ".if" statementnon-constant fill count for absolute sectionnon-contiguous register rangenon-immediate OPF operand, ignorednon-pc-relative relocation for pc-relative fieldnot a 16 bit instruction '%s'not enough operands (%d) for '%s'; expected %dnot using any base registernumber (0x%s) larger than 32 bitsnumber larger than 64 bitsnumber must be positive and less than %dnumber of literal tokens != 1number of operands mismatchnumber of registers must be in the range [1:4]numeric view can only be asserted to zeroodd address operand: %ldodd displacement at %xodd distance branch (0x%lx byte)odd distance branch (0x%lx bytes)odd number cannot be used hereodd number of bytes in operand descriptionodd numbered general purpose register specified as register pairodd register cannot be used hereoffset and base must be from the same unitoffset has different size from baseoffset in operand %u of '%.*s' not divisible by %uoffset in operand %u of '%.*s' out of rangeoffset must be a multiple of %doffset must be zero in ARM encodingoffset not a multiple of 4offset out of rangeoffset register expectedoffset to unaligned destinationoffset too largeoffset value out of rangeonly 'LSL' shift is permittedonly 'MUL VL' is permittedonly 'MUL' is permittedonly D registers may be indexedonly LSL shift allowed in thumb modeonly SUBS PC, LR, #const allowedonly constant expression allowedonly constant offsets supported in absolute sectiononly floating point zero is allowed as immediate valueonly lo regs allowed with immediateonly lower 16-bits of first operand are usedonly one type should be specified for operandonly r0 can be used as byte count registeronly r0.bX byte fields of r0 can be used as byte countonly r15 allowed hereonly single block types allowedonly supported with old gcconly two consecutive VFP SP registers allowed hereopcode %s not found in opcode hash tableopcode '%s' not supported for target %sopcode '%s': cannot find literal definitionopcode '%s': could not parse operand '%s' in '%s'opcode '%s': no bound opname '%s' for precondition in '%s'opcode '%s': precondition only contains constants in '%s'opcode '%s': replacement does not have %d opopcode '%s': replacement does not have %d opsopcode '%s': unidentified operand '%s' in '%s'opcode 'NOP.N' unavailable in this configurationopcode `%s' not supported for target %sopcode has no effectopcode missing or not found on input lineopcode not supported in the `insn32' modeopcode not supported in the `insn32' mode `%s'opcode not supported on this processor: %s (%s)opcode not valid for this cpu variantopcode-specific %s relocation used outside an instructionopcodes '%s' (slot %d) and '%s' (slot %d) both have volatile port accessesopcodes '%s' (slot %d) and '%s' (slot %d) write the same portopcodes '%s' (slot %d) and '%s' (slot %d) write the same registeropcodes '%s' (slot %d) and '%s' (slot %d) write the same stateopen CFI at the end of file; missing .cfi_endproc directiveoperandoperand %d must be %s -- `%s'operand %d must be an immediateoperand %d must be an immediate expressionoperand %d must be constantoperand %d must be scalaroperand %d must be the same register as operand 1 -- `%s'operand %d of '%s' has invalid value '%u'operand %d of '%s' has out of range value '%u'operand %d out of rangeoperand %d overlap in %soperand %d: illegal use expression: `%s`operand %s0x%lx out of range.operand %u of '%.*s' is read-onlyoperand %u of '%.*s' is write-onlyoperand %u of '%.*s' not a valid base address registeroperand %u of '%.*s' not a valid memory referenceoperand %u of '%.*s' not a valid return address registeroperand %u of '%.*s' not constantoperand %u of '%.*s' on wrong sideoperand %u of '%.*s' out of rangeoperand 1 must be FPSCRoperand index error for %soperand is not an absolute constantoperand is not an immediateoperand mask overflowoperand mismatch -- `%s'operand must be a constantoperand must be a constant or a labeloperand must be a multiple of 2operand must be a multiple of 4operand must be absolute in range %lx..%lx, not %lxoperand must be absolute in range %u..%u, not %ldoperand not a multiple of 4 for PT, PTA or PTB: %doperand number mismatchoperand out of rangeoperand out of range (%d is not between %d and %d)operand out of range (%s not between %ld and %ld)operand out of range for PT, PTA and PTBoperand out of range, instruction expandedoperand out of range: %ldoperand out of range: %luoperand out of range: 0x%lxoperand overflowoperand references R%ld of instruction before previous.operand references R%ld of previous instruction.operand references R%ld of previous load.operand size mismatchoperand size must be specified for immediate VMOVoperand size must match register widthoperand type mismatchoperand types can't be inferredoperand value out of range for instructionoperand/size mis-matchoperands 0 and 1 must be the same registeroperands for opcode `%s' do not match any valid formatoperands mismatchoperands were not reducible at assembly-timeoperation combines symbols in different segmentsoption --link-relax is only supported in b.out formatoption `%s' may not be negatedoption `%s' not recognizedoption `-%c%s' is deprecated: %soption `-A%s' is deprecated: use `-%s'or higherout of memoryout of rangeoutput verbose error messagesoverflowoverflow in branch to %s; converted into longer instruction sequenceoverflow in immediate argumentoverflow in literal (.lit8) tableoverflow in literal (.lita) tablep2align not supported on this targetpacking conflict: %s must dispatch sequentiallypadding addedparallelparallel instruction not following another instructionparentheses ignoredparse errorpc may not be used with write-backpc-relative pc-relative address offset out of rangepc-relative load offset not word alignedpc-relative load offset out of rangepce instruction error (16 bit || 16 bit).pcrel for branch to %s too far (0x%lx)pcrel for branch to %s too far (0x%x)pcrel for loopt too far (0x%lx)pcrel for lrw/jmpi/jsri to %s too far (0x%lx)pcrel relocation not allowed in an instructionpcrel too farpcrel too far BFD_RELOC_BFIN_10pcrel too far BFD_RELOC_BFIN_11_PCRELpcrel too far BFD_RELOC_BFIN_12pcrel too far BFD_RELOC_BFIN_24pcrel too far BFD_RELOC_BFIN_5pcrel too far BFD_RELOC_MOXIE_10personality routine required before .handlerdata directivepersonality routine specified for cantunwind framepointer register (X, Y or Z) requiredpointer register (Y or Z) requiredpointer register Z requiredpolymorphs are not enabled. Use -mP option to enable.post-index must be a registerpost-indexed expression used in preload instructionpostincrement not supportedpowerpc_operands[%d] duplicates powerpc_operands[%d]powerpc_operands[%d].bitm invalidpre-indexed expression expectedpredicate not followed by instructionpredication on A0 not supported on this architectureprefer-const16 conflicts with prefer-l32rprefer-l32r conflicts with prefer-const16premature end of floating point prefixprevious .ent not closed by a .endprevious CFI entry not closed (missing .cfi_endproc)previous movx requires nopyprevious movy requires nopxprofiling in absolute section?pseudo instruction `%s' not supportedpseudo prefix without instructionpseudo-op illegal within .struct/.unionpush/pop do not support {reglist}^qualifying predicate not followed by instructionquick branch offset %d out of range %d to %dr12 not allowed herer13 not allowed herer14 not allowed as first register when second register is omittedr14 not allowed herer15 based store not allowedr15 not allowed herer2 should not be used in indexed addressing moder31 cannot be used with jmp; use ret insteadr31 cannot be used with jmpr.n; use ret.n insteadrd must be even number.rdhi and rdlo must be differentrdhi, rdlo and rm must all be differentre-entrant coderecord type is not validrecord_type_not_validredefined symbol cannot be used on relocredefinition of global registerredefinition of mcu type `%s' to `%s'redundant %s prefixreg should <= 31reg-reg expectedregister expectedregister expected, but saw '%.6s'register expected, not '%.100s'register is out of orderregister is wrong size for a word %sregister is wrong size for address %sregister list must be even numberedregister list must be from the same unitregister list must contain at least 1 and at most 16 registersregister list must not contain duplicatesregister list not in ascending orderregister must be either sp or set by a previousunwind_movsp directiveregister name or number from 0 to 31 requiredregister name or number from 16 to 31 requiredregister number %u not supported on this architectureregister number above 15 requiredregister number out of rangeregister number too large for push/popregister offset not allowed in pre-indexed addressing moderegister operand expected, but got scalarregister out of range in listregister pair for operand %u of '%.*s' not a valid even/odd pairregister r%d out of rangeregister r0 cannot be used hereregister r16-r23 requiredregister r24, r26, r28 or r30 requiredregister range not in ascending orderregister rh%d out of rangeregister rl%d out of rangeregister rq%d does not existregister rq%d out of rangeregister rr%d does not existregister rr%d out of rangeregister same as write-back baseregister save offset not a multiple of %uregister scaling is being ignored hereregister section has contents register stride must be 1 or 2register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}register type mismatchregister unit must be one of %sregister value used as expressionregisters may not be the samerel too far BFD_RELOC_16rel too far BFD_RELOC_8rel31 relocation overflowrelative address out of rangerelative call out of rangerelative jump out of rangerelax hint unrecognized instruction: line %d.relaxation not supported relaxed out-of-range branch into a jumpreloc %d not supported by object file formatreloc not within (fixed part of) sectionrelocated field and relocation type differ in signednessrelocation %s isn't supported by the current ABIrelocation cannot be done when using -mrelocatablerelocation is not supportedrelocation not allowedrelocation not applicablerelocation out of rangerelocation overflowrelocation valid in thumb1 code onlyrepeat < 0; .fill ignoredrepeat count cannot be used with %srepeat instruction used with non-register mode instructionrequired displacement wasn't given in indirect referenceresidual low bits in pmem diff relocationresource conflict (A%d)resource conflict (C flag)resource conflict (F flag)resource conflict (PSW)resource conflict (R%d)rest of line ignored; first ignored character is `%c'restore without savereturned from mips_ip(%s) insn_opcode = 0x%x right operand is a bignum; integer 0 assumedright operand is a float; integer 0 assumedror #imm not supportedrotation can only be 0, 8, 16, or 24rounding down first operand float to signed introunding down first operand float to unsigned intrva without symbols suffix on comparison instruction is deprecateds3_PIC code offset overflow (max 16 signed bits)same type of prefix used twicescalar index must be constantscalar index out of rangescalar must have an indexscalar out of rangescalar out of range for multiply instructionscale factor invalid on this architecture; needs cpu32 or 68020 or higherscale factor of %d without an index registerscore3d instruction.sdaoff() relocation used on an instruction which does not support itsecondsecond .ent directive found before .end directivesecond operand missingsecond operand must be 1second operand of .insn not a constant second register should be greater than first registersecond register should follow dash in register listsection %s renamed multiple timessection '%s' finished with an open IT block.section `%s' aliased to `%s' is not usedsection alignment must be >= 4 bytes to check MULS/MULU safenesssection change from within a BSPEC/ESPEC pair is not supportedsection symbols are already globalseek to end of .incbin file failed `%s'segment override on `%s' is ineffectualselected FPU does not support instructionselected architecture does not support wide conditional branch instructionselected processor does not have all features of selected architectureselected processor does not support 'A' form of this instructionselected processor does not support 32bit wide variant of instruction `%s'selected processor does not support ARM opcodesselected processor does not support DSP extensionselected processor does not support PSTATE field name '%s'selected processor does not support SETPAN instructionselected processor does not support THUMB opcodesselected processor does not support `%s'selected processor does not support `%s' in ARM modeselected processor does not support `%s' in Thumb modeselected processor does not support `%s' in Thumb-2 modeselected processor does not support fp16 instructionselected processor does not support requested special purpose registerselected processor does not support system register name '%s'selected target format '%s' unknownsequence number in use for !tlsgd!%ldsequence number in use for !tlsldm!%ldsequentialset can only use RD port as sourceset: number not in -2147483648..4294967295 rangeset: number not in 0..4294967295 rangesetend use is deprecated for ARMv8setsw: number not in -2147483648..4294967295 rangesetting incorrect section attributes for %ssetting incorrect section type for %ssetx: illegal temporary register g0setx: temporary register same as destination registershift amount out of range 0 to 63shift by register not allowed in thumb modeshift countshift expression expectedshift expression is too largeshift must be constantshift not allowed for bitmask immediateshift operator expectedshift out of rangeshift value over 3 not allowed in thumb modeshifts in CMP/MOV instructions are only supported in unified syntaxshort branch with zero offset: use :wshortcut designator invalidshould have 1 or 2 operandsshould have two operandssigned .word overflow; switch may be too large; %ld at 0x%lxsigned value out of rangesimd instructions operate on pair values (L prefix)single instruction is %u bytes long, but .bundle_align_mode limit is %u bytessize (%ld) out of range, ignoredsize is not 4 or 6size negative; .fill ignoredsize of "%s" is already %ld; not changing to %ldsize value for space directive too large: %lxskip (%ld) or count (%ld) invalid for file size (%ld)skipping prefixes on this instructionskipping two-word instructionsmi pseudo instruction should not use a label in imm fieldsome symbol undefined; zero assumedsourcesource and address units must not be shared for this addressing modesource and destination increment mode must agreesource and destination must be differentsource and destination register must be in different unitssource operand must be 16bit absolute addresssource operand must be 8 bit registersource register must be in the trigger unitsource register must be r1source register same as write-back basesource register should be even numberedsource registers should be even numberedsource1 and dest must be same registerspace allocation too complex in absolute sectionspace allocation too complex in common sectionsparc convert_frag special left instruction `%s' kills instruction `%s' in right containerspecified location wasn't TETRA-alignedspill_mask record unimplemented.spu convert_frag spurious operands; (%d operands/instruction max)st/ld offset 23 instruction was disabled .stack frame layout does not match personality routinestack frame layout too complex for unwinderstack increment must be multiple of 4stack pointer offset too large for personality routinestand-alone `%s' prefixstart address not supportedstrange paper height, set to no formstray `\'stride must be a multiple of 64; lower 6 bits ignoredstride of 2 unavailable when element size is 8string too big (%lu bytes)strings must be placed into a sectionsupport ARM/Thumb interworkingswp{b} use is deprecated for ARMv6 and ARMv7swp{b} use is obsoleted for ARMv8 and latersymbol "%s" undefined; zero assumedsymbol %s is in a different sectionsymbol %s is weak and may be overridden latersymbol '%s' is already definedsymbol `%s' aliased to `%s' is not usedsymbol `%s' already definedsymbol `%s' can not be both weak and commonsymbol `%s' is already definedsymbol `%s' is already defined as "%s"/%s%ldsymbol definition loop encountered at `%s'symbol in .toc does not match any .tcsymbol name not recognised in the current localesymbol size computation overflowsymbol too far awaysymbol type "%s" is supported only by GNU and FreeBSD targetssymbol type "%s" is supported only by GNU targetssymbol%dsymbol+offset not supported for got tlssymbolic operand not allowedsymbols assigned with .asg must begin with a lettersymbols assigned with .eval must begin with a lettersyntax errorsyntax error in .startof. or .sizeof.syntax error in @(disp,[Rn, gbr, pc])syntax error in @(r0,...)syntax error in @(r0...)syntax error in structured control directivesyntax error: condition code not expectedsyntax error: expected `]', found `%c'syntax error: invalid toc specifier `%s'syntax error: register not expectedsyntax error: system register not expectedsyntax error: value is missing before the register namesyntax error: vector register not expectedsyntax error; ')' not allowed heresyntax error; end of line, expected `%c'syntax error; expected ','syntax error; found `%c', expected `%c'syntax error; missing '(' after displacementsyntax error; missing ')' after base registersystem register name '%s' is deprecated and may be removed in a future releasesystem registers cannot be included in listtag not found for .tag %starget of %s instruction must be a labeltarget out of rangetdaoff() relocation used on an instruction which does not support ittemporary switch for dumpingtext label `%s' aligned to odd boundarythe %d-bit %s architecture does not support the `%s' extensionthe %s name '%s' is too long (maximum 16 characters)the XCOFF file format does not support arbitrary sectionsthe `%s' extension requires %s%d revision %d or greaterthe `%s' extension requires 64-bit FPRsthe `%s' extension was removed in %s%d revision %dthe number of .indirect_symbols defined in section %s does not match the number expected (%d defined, %d expected)the offset 0x%08lX is not representablethe only valid suffixes here are '(plt)' and '(tlscall)'the optional immediate offset can only be 0the second source register `%s%s' implicitly denotes `%s%.3s%d' to `%s%.3s%d' source group in `%s'the source register must not be $0the source register must not be $31the specified option is not accepted for PSBthe specified option is not accepted in ISBthe specified relocation type is not allowed for 32-bit registerthe specified relocation type is not allowed for MOVKthe top half of a 128-bit FP/SIMD register is expectedthe type of %s is too complex; it will be simplifiedthe use of -mvle requires -a32.the use of -mvle requires big endian.the yielding instruction %s may not be in a delay slot.there are no pc-relative size relocationsthere are no unsigned pc-relative relocationsthirdthis DS form not yet supportedthis addressing mode is not applicable for destination operandthis addressing mode requires base-register writebackthis group relocation is not allowed on this instructionthis instruction does not accept an accumulatorthis instruction does not accept an immediatethis instruction does not support indexingthis instruction implies use of ARMv8.1 AdvSIMD.this instruction requires a post-indexed addressthis instruction will not write back the base registerthis instruction will write back the base registerthis relocation modifier is not allowed on this instructionthis string may not contain '\0'this type of register can't be indexedthumb conditional instruction should be in IT blocktoo few operandstoo many !literal!%ld for %stoo many .dim entriestoo many .size entriestoo many GREG registers allocated (max %d)too many IVC2 insns to pack togethertoo many IVC2 insns to pack with a 16-bit core insntoo many IVC2 insns to pack with a 32-bit core insntoo many argumentstoo many fixupstoo many instructions in execute packettoo many lda insns for !gpdisp!%ldtoo many ldah insns for !gpdisp!%ldtoo many lituse insns for !lituse_tlsgd!%ldtoo many lituse insns for !lituse_tlsldm!%ldtoo many memory references for `%s'too many operandstoo many operands (%d) for '%s'; expected %dtoo many operands in instructiontoo many operands to '%.*s'too many positional argumentstoo many registers in vector register listtoo many st_End'stoo many unwind opcodestoo many unwind opcodes for personality routine 0too many unwinding instructionstrailing garbage after expression: %stranslating bgeni to movitranslating bmaski to movitranslating mgeni to movitranslating to `%s %s%s'translating to `%s %s%s,%s%s'translating to `%sp'trap exception not supported at ISA 1tried to set unrecognized symbol: %s truncated file `%s', %ld of %ld bytes readtwo .function pseudo-ops with no intervening .eftype %d reloc done? type mismatch in vector register listtype specifier has the wrong number of partstypes specified in both the mnemonic and operandsunable to compute ADRL instructions for PC offset of 0x%lxunable to continue with assembly.unable to generate unwinding opcode for frame pointer offsetunable to generate unwinding opcode for frame pointer reg %dunable to generate unwinding opcode for reg %dunable to locate include file: %sunable to pack %s by itself?unable to rebuffer file: %s unable to repeat %s insnunable to restore return address from previously restored regunable to widen instructionunaligned branch target: %d bytes at 0x%lxunaligned data at an absolute location is not supportedunaligned entry instructionunaligned loop: %d bytes at 0x%lxunaligned registerunassigned file number %ldunbalanced brackets in operand %d.unbalanced parenthesis in operand %d.unclosed '('undecodable fixundecodable instruction in instruction fragundefined combination of operandsundefined local label `%s'undefined symbol %s in PCR relocationundefined symbol %s used as an immediate valueundefined symbol for opcode "%s"unexpected %s fixupunexpected .cantunwind directiveunexpected .cfi_inline_lsdaunexpected .handlerdata directiveunexpected .unwind_movsp directiveunexpected 12-bit reloc typeunexpected 18-bit reloc typeunexpected PC relative expressionunexpected TLS relocationunexpected `"' in expressionunexpected addressing mode for %sunexpected bit specified after APSRunexpected character `%c' in element sizeunexpected character `%c' in predication typeunexpected character `%c' in type specifierunexpected characters following instructionunexpected comma after the mnemonic name `%s' -- `%s'unexpected comma before the omitted optional operandunexpected end of file in irp or irpcunexpected end of file in macro `%s' definitionunexpected end of lineunexpected fixunexpected negative constantunexpected register in the immediate operandunexpected section size informationunexpected shift operatorunexpected storage class %dunhandled %d unhandled CFA insn for unwinding (%d)unhandled local relocation fix %sunhandled operand code %dunhandled reloc %s in md_pcrel_from_sectionunhandled relocation type %sunhandled: .proc %s,%dunimplemented opcode "%s"unimplemented relocation suffixunimplemented segment %s in operandunimplemented toc32 expression modifierunimplemented toc64 expression modifierunindexed addressing used in preload instructionunknownunknown -mpid= argument '%s'unknown .gnu_attribute valueunknown .loc sub-directive `%s'unknown ABI version`%s' unknown DSP `%s'unknown DSP prefix character %c %sunknown EABI `%s' unknown FPU configuration `%s' unknown ISA level %sunknown ISA or architecture %sunknown MCU: %s unknown abi `%s' unknown addressing mode %sunknown arch name `%s' unknown architectural extension `%s'unknown architectureunknown architecture %sunknown architecture '%s'unknown architecture `%s' unknown architecture extension `%s' unknown architecture: %s unknown argument for .usepvunknown baseline `%s' unknown condition code: %sunknown constraint `%c'unknown cpu `%s'unknown default cpu = %s, os = %sunknown directiveunknown escape '\%c' in string; ignoredunknown execution type passed to write_2_short()unknown expression in operand %sunknown expression in operand %s. Use #llo(), #lhi(), #hlo() or #hhi()unknown fixup sizeunknown floating point abi `%s' unknown floating point format `%s' unknown floating point mnemonic: "%s"unknown floating point prefix characterunknown floating type type '%c'unknown fpu `%s'unknown group relocationunknown implicit IT mode `%s', should be arm, thumb, always, or never.unknown instruction '%s'unknown interrupt %sunknown mnemonic `%s' -- `%s'unknown mnemonic: "%s"unknown opcodeunknown opcode "%s"unknown opcode %sunknown opcode '%s'unknown opcode `%s'unknown opcode or format name '%s'unknown opcode: %sunknown opcode: `%s'unknown operand %sunknown operand countunknown operand shift: %x unknown operand to .archunknown operator %s. Did you mean X(Rn) or #[hl][hl][oi](CONST) ?unknown or invalid section attribute '%s'unknown or invalid section type '%s'unknown or missing PSTATE field nameunknown or missing operation nameunknown or missing option to PSBunknown or missing system register nameunknown parameter following .SECTION directive: %sunknown procedure kindunknown profiling flag - ignored.unknown pseudo-op: `%s'unknown record type %d (in %s)unknown register %sunknown register '%s' -- .req ignoredunknown register `%s'unknown register alias '%s'unknown relocation (%u)unknown relocation modifierunknown section attribute %sunknown section attribute '%c'unknown user-defined function %sunknown vector operation: `%s'unknown width specifier '.%c'unknown/incorrect operandunmatched '['unmatched .end directiveunpredictable DCTI coupleunpredictable load of register pair -- `%s'unpredictable transfer with writeback -- `%s'unrecognised RX CPU type %sunrecognised alignment value in .SECTION directive: %sunrecognised argument to -mcpu option '%s'unrecognised cpu type '%s'unrecognised instruction %sunrecognised instruction size modifier .%cunrecognized %d-bit version of microMIPS opcodeunrecognized .linkonce type `%s'unrecognized .section attribute: want a,e,w,x,M,S,G,T or numberunrecognized CPS flagunrecognized characters at end of parallel processing insnunrecognized default cpu `%s'unrecognized emulation name `%s'unrecognized extended version of MIPS16 opcodeunrecognized flagunrecognized fopt optionunrecognized opcodeunrecognized opcode: `%s'unrecognized option "%s"unrecognized option -%c%sunrecognized pseudo-instruction %sunrecognized register name `%s'unrecognized reloc typeunrecognized relocation suffixunrecognized section attributeunrecognized section command `%s'unrecognized section typeunrecognized section type `%s'unrecognized stab type '%c'unrecognized symbol suffixunrecognized symbol type "%s"unrecognized syntax mode "%s"unrecognized unextended version of MIPS16 opcodeunresolvable or nonpositive repeat count; using 1unresolved expression that must be resolvedunresolved loop target symbol: %sunshifted register requiredunsigned value out of rangeunsupported BFD relocation size %dunsupported BFD relocation size %uunsupported DC typeunsupported alignmentunsupported alignment for instructionunsupported broadcastunsupported byte value; use a different suffixunsupported constant in relocationunsupported constant size %d unsupported fixup size %dunsupported flag %i in line directiveunsupported fptr fixupunsupported fptr fixup size %dunsupported instruction `%s'unsupported large constantunsupported maskingunsupported mbind section info: %sunsupported relocationunsupported relocation against %sunsupported relocation for DS offset fieldunsupported relocation typeunsupported section attribute '%c'unsupported section attribute -- 'a'unsupported static rounding/saeunsupported symbol subtractionunsupported syntaxunsupported use of %sunsupported use of .ehwordunsupported use of .gpdwordunsupported use of .gpwordunsupported variable size or fill valueunsupported vector index registerunsupported with Intel mnemonicunterminated stringunterminated string; newline inserteduntil without repeatunwind opcode too longunwound frame has negative sizeunwound stack pointer not doubleword aligneduse -march=armv2use -march=armv2ause -march=armv3use -march=armv3muse -march=armv4use -march=armv4tuse -march=armv5use -march=armv5tuse -march=armv5teuse -mcpu=alluse -mcpu=arm1use -mcpu=arm2use -mcpu=arm250use -mcpu=arm3use -mcpu=arm6use -mcpu=arm600use -mcpu=arm610use -mcpu=arm620use -mcpu=arm7use -mcpu=arm70use -mcpu=arm700use -mcpu=arm700iuse -mcpu=arm710use -mcpu=arm7100use -mcpu=arm710cuse -mcpu=arm710tuse -mcpu=arm720use -mcpu=arm720tuse -mcpu=arm740tuse -mcpu=arm7500use -mcpu=arm7500feuse -mcpu=arm7duse -mcpu=arm7diuse -mcpu=arm7dmuse -mcpu=arm7dmiuse -mcpu=arm7muse -mcpu=arm7tdmiuse -mcpu=arm8use -mcpu=arm810use -mcpu=arm9use -mcpu=arm920use -mcpu=arm940use -mcpu=arm9tdmiuse -mcpu=iwmmxtuse -mcpu=strongarmuse -mcpu=strongarm110use -mcpu=strongarm1100use -mcpu=strongarm1110use -mcpu=xscaleuse -mfpu=fpa10use -mfpu=fpa11use -mfpu=fpeuse .code16 to ensure correct addressing modeuse either -mfpu=softfpa or -mfpu=softvfpuse frame pointeruse of .indirect_symbols requires `-dynamic'use of PC in this instruction is deprecateduse of old and new-style options to set CPU typeuse of old and new-style options to set FPU typeuse of r13 is deprecateduse of r15 in blx in ARM mode is not really usefuluse of r15 in bx in ARM mode is not really usefuluse of r15 in bxj is not really usefuluse stack size checkingused $%u with ".set at=$%u"used $at without ".set noat"using using `%s%s' instead of `%s%s' due to `%c' suffixusing a bit field width of zerovalid endian specifiers are be or levalue %d out of range. Use #lo() or #hi()value %ld out of rangevalue 0x%I64x truncated to 0x%I64xvalue 0x%llx truncated to 0x%llxvalue 0x%lx truncated to 0x%lxvalue 0x%x out of extended range.value not in range [-0xffffffff, 0xffffffff]value not in range [0, 0x7fffffff]value not in range [0, 0xffffffff]value of %ld out of byte displacement range.value of %ld out of double word displacement range.value of %ld out of word displacement range.value of %ld too large for 16-bit branchvalue of %ld too large for 8-bit branchvalue of %s too large for field of %d byte at %svalue of %s too large for field of %d bytes at %svalue out of rangevalue out of range: 0x%xvalue stored for r%d is UNKNOWNvalue too large for 1-byte fieldvalue too large for 2-byte fieldvalue too large to fit in %d bitsvector element must be constantvector register expectedvector type expectedvfmal/vfmsl with FP16 type cannot be conditional, the behaviour is UNPREDICTABLEview number mismatchvirtual memory exhaustedvliw group must consist of 1 core and 1 copro insn.warn about symbols that match instruction names [default]warning: symbol %s has no csectwasm32 assembler options: width suffixes are invalid in ARM modewidth suffixes are invalid in ARM mode -- `%s'word of NOPs added between word multiply and 16-bit multiplyword of NOPs added between word multiply and loadwriteback (!) must be used for VLDMDB and VSTMDBwriteback of base register is UNPREDICTABLEwriteback of base register when in register list is UNPREDICTABLEwriteback used in preload instructionwriteback value must be an immediate constantwriting or modifying # is unpredictablewriting to APSR without specifying a bitmask is deprecatedwrong argument to .cfi_personality_idwrong number of operandswrong number of operands for '%s'wrong register in floating-point reglistwrong second argument to .cfi_lsdawrong second argument to .cfi_personalitywrong size instruction in a %u-bit branch delay slotwrong third argument to .cfi_val_encoded_addrxtensa-isa failure: %syou can't `pop %scs'you must specify a single type onlyyou must use a hi/lo directive or 16-bit macro to load a 16-bit value.zdaoff() relocation used on an instruction which does not support itzero assumed for missing expressionzero flag is not valid for this instructionzero used as immediate valuezeroing-masking only allowed with write mask{standard input}Project-Id-Version: gas-2.30.0 Report-Msgid-Bugs-To: [email protected] POT-Creation-Date: 2018-01-13 13:44+0000 PO-Revision-Date: 2018-01-15 21:02+0100 Last-Translator: FrÃ©dÃ©ric Marchal Language-Team: French Language: fr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Bugs: Report translation errors to the Language-Team address. Plural-Forms: nplurals=2; plural=(n >= 2); mode de compatibilitÃ© avec la syntaxe TI CodeComposer Studio [dÃ©faut est %d] [dÃ©faut est %s] spÃ©cifier la variante d'architecture 960 -b ajouter du code pour la cueillette de statistiques au sujet des branchements utilisÃ©s -link-relax prÃ©server les directives individuelles pour que l'Ã©diteur de lien puisse faire la relaxe (format b.out seulement) -no-relax ne pas altÃ©rer les instructions comparer-et-aiguiller pour les longs dÃ©placements spÃ©cifier la variante d'architecture SPARC -bump avertir lorsque l'assembleur change d'architecture -sparc ignorÃ© --enforce-aligned-data forcer .long, etc., Ã Ãªtre alignÃ©s correctement -relax relaxer les jump et les branchements (par dÃ©faut) -no-relax Ã©viter les modifications des jump et des branchements %s Options assembleur spÃ©cifiques NDS32Â : fichier d'entrÃ©e : %s options passÃ©es : fichier de sortie : %s cible : %s horodatage : %s -no-relax ne pas relaxer les rÃ©adressages Option D30V: -O Rendre le instructions adjacentes courtes parallÃ¨les si possible. -n Avertir pour tous les NOP insÃ©rÃ©s par l'assembleur. -N Avertir pour tous les NOP insÃ©rÃ©s aprÃ¨s des mots multiples -c Avertir pour tous les symboles ayant des noms identiques aux noms de registres -C Inverse de -c. -c est le dÃ©faut. Options TIC4X: -mcpu=CPU -mCPU sÃ©lectionner la variante d'architecture. CPU peut valoir: 30 - TMS320C30 31 - TMS320C31, TMS320LC31 32 - TMS320C32 33 - TMS320VC33 40 - TMS320C40 44 - TMS320C44 -mrev=REV sÃ©lectionner la rÃ©vision hardware du cpu (nombres entiers). Combinaisons de -mcpu et -mrev vont activer/dÃ©sactiver les options appropriÃ©es (-midle2, -mlowpower et -menhanced) en fonction du type sÃ©lectionnÃ© -mbig sÃ©lectionner le grand modÃ¨le mÃ©moire -msmall sÃ©lectionner le petit modÃ¨le mÃ©moire(par dÃ©faut) -mregparm sÃ©lectionner les paramÃ¨tres via registres (par dÃ©faut) -mmemparm sÃ©lectionner les paramÃ¨tres via mÃ©moire -midle2 activer le support IDLE2 -mlowpower activer le support LOPOWER et MAXSPEED -menhanced activer le support des opcodes Ã©tendus des violations de contraintes pour des violations de contraintes parallÃ¨les pourraient violer les contraintes pourraient violer les contraintes EXTENSION est une combinaison de: Registres n'ont pas besoin de prÃ©fixe Registres auront besoin du prÃ©fixe Â«Â $Â Â» Ã©muler la sortie (par dÃ©faut %s) Enregistrer le type de cpu -EB assembler le code pour un systÃ¨me de poids fort -EL assembler le code pour un systÃ¨me de poids faible -FIXDD corriger la dÃ©pendance des donnÃ©es -G gpnum assembler le code pour le paramÃ¨tre gpsize, le dÃ©faut est 8 octets -KPIC gÃ©nÃ©rer du code indÃ©pendant de la position -NWARN ne pas afficher d'avertissement pour des corrections de dÃ©pendance de donnÃ©es -O0 ne faire aucune optimisation -SCORE3 assembler le code pour une cible SCORE3 -SCORE5 assembler le code pour une cible SCORE5 -SCORE5U assembler le code pour une cible SCORE5U -SCORE7 assembler le code pour une cible SCORE7 [dÃ©faut] -USE_R1 assembler le code sans avertissement lorsque le registre temporaire r1 est utilisÃ© -V version de distribution Sunplus -V afficher la version de l'assembleur -Qy, -Qn ignorÃ© -march=score3 assembler le code pour une cible SCORE3 -march=score7 assembler le code pour une cible SCORE7 [dÃ©faut] Options S390: -mregnames Permettre les noms symboliques pour les registres -mwarn-areg-zero Avertir lorsque des registres de base/index Ã zÃ©ro -mno-regnames Ne pas permettre les noms symboliques pour les registres -m31 DÃ©finir le format de fichier Ã 32 bits -m64 DÃ©finir le format de fichier Ã 64 bits ops Ã©tait: %s vouliez-vous dire ceciÂ ? autre(s) variante(s) valide(s)Â : --32/--64/--x32 gÃ©nÃ©rer du code 32 bits/64 bits/x32 --MD FICHIER Ã©crire les information de dÃ©pendance dans le FICHIER (par dÃ©faut aucun) --alternate active dÃ¨s le dÃ©part la syntaxe alternÃ©e des macros --compress-debug-sections[={none|zlib|zlib-gnu|zlib-gabi}] compresser les sections DWARF de dÃ©bug avec zlib --compress-debug-sections[={none|zlib|zlib-gnu|zlib-gabi}] compresser les sections DWARF de dÃ©bug avec zlib [par dÃ©faut] --debug-prefix-map ANCIEN=NOUVEAU remplace ANCIEN par NOUVEAU dans les informations de dÃ©bug --defsym SYMBOLE=VALEUR dÃ©finir le SYMBOLE avec cette valeur --disp-size-default-22 dÃ©placement de branchement sans taille connue est de 22 bits (par dÃ©faut) --disp-size-default-32 dÃ©placement de branchement sans taille connue est de 32 bits --divide ne traite pas Â«Â /Â Â» comme un caractÃ¨re de commentaire --divide ignorÃ© --elf-stt-common=[no|yes] gÃ©nÃ©rer les symboles commun ELF avec le type STT_COMMON --execstack requiert une pile exÃ©cutable pour cet objet --fatal-warnings traiter les avertissements comme des erreurs --fix-v4bx Autoriser BX dans du code ARMv4 --gdwarf-2 gÃ©nÃ©rer les informations de dÃ©bug DWARF2 --gdwarf-sections gÃ©nÃ©rer des noms de sections par fonction pour les informations de lignes DWARF --gstabs gÃ©nÃ©rer les informations STABS de dÃ©bug --gstabs+ gÃ©nÃ©rer les infos STABS de dÃ©bug avec les extensions GNU --hash-size= fixer la taille de la table de hash proche de --help afficher l'aide-mÃ©moire et quitter --itbl INSTTBL Ã©tendre le jeu d'instructions pour inclure les instructions concordants avec les spÃ©cifications dÃ©finies dans le fichier INSTTBL --listing-cont-lines initialiser le nombre maximal de lignes de continuation Ã utiliser pour la colonne de donnÃ©e en sortie dans le listing --listing-lhs-width initialiser la largeur en mots de la colonne de donnÃ©es en sortie sur le listing --listing-lhs-width2 initialiser la largeur en mots des lignes de continuation de la colonne de donnÃ©es en sortie; ignorÃ© si plus petit que la largeur de la premiÃ¨re ligne --listing-rhs-width initialiser la largeur maximale en caractÃ¨res des lignes du fichier source --m32bit-doubles [par dÃ©faut] --m32bit-doubles [par dÃ©faut] --m64bit-doubles --m64bit-doubles Le code source utilise des doubles 64 bits --march= GÃ©nÃ©rer le code pour . Choix possibles pour sont v0_v10, v10, v32 et common_v10_v32. --mbig-endian-data --mcpu= --mg10 Activer le support pour la variante G10 --mg13 SÃ©lectionner le cÅ“ur G13. --mg14 SÃ©lectionner le cÅ“ur G14 [dÃ©faut] --mint-register= --mlittle-endian-data [par dÃ©faut] --mno-allow-string-insns --mpid --mrelax --mrelax permettre la relÃ¢che lors de l'Ã©dition de liens --mrl78 Alias pour -mg14 --msmall-data-limit --muse-conventional-section-names --muse-renesas-section-names [par dÃ©faut] --no-underscore Les symboles utilisateurs n'ont pas de prÃ©fixe --nocompress-debug-sections ne pas compresser les sections de dÃ©bug DWARF --nocompress-debug-sections ne pas compresser les sections de dÃ©bug DWARF [par dÃ©faut] --noexecstack ne requiert pas de pile exÃ©cutable pour cet objet --pic Permettre la gÃ©nÃ©ration de code indÃ©pendant de la position. --reduce-memory-overheads favoriser l'utilisation rÃ©duite de la mÃ©moire au dÃ©triment d'un temps d'assemblage accru --sectname-subst activer les sÃ©quences de substitution de noms de sections --size-check=[error|warning] vÃ©rifier la directive ELF .size (par dÃ©faut --size-check=error) --statistics afficher diverses mesures de statistiques de l'exÃ©cution --strip-local-absolute Ã©liminer les symboles absolus locaux --target-help montrer les options spÃ©cifiques de la cible --traditional-format utiliser le mÃªme format que l'assembleur natif lorsque c'est possible --underscore Symboles utilisateurs sont normalement prÃ©fixÃ©s avec le caractÃ¨re de soulignement. --version afficher le numÃ©ro de la version de l'assembleur et quitter --warn ne pas supprimer les avertissements -D produire les messages de dÃ©bug assembleur -EB assembler le code pour un systÃ¨me de poids fort -EB assembler pour un systÃ¨me gros boutiste (dÃ©faut) -EL assembler pour un systÃ¨me petit boutiste -EB,-big produire du code et des donnÃ©es pour systÃ¨mes Ã octets de poids fort -EL gÃ©nÃ©rer du code pour un systÃ¨me Ã octets de poids faible (par dÃ©faut) -EB gÃ©nÃ©rer du code pour un systÃ¨me Ã octets de poids fort -mwarn-expand avertir si des pseudo opÃ©rations sont Ã©tendues -mxp activer le support pour i860XP (dÃ©sactivÃ© par dÃ©faut) -mintel-syntax activer la syntaxe Intel (dÃ©faut: AT&T/SVR4) -EL assembler le code pour un systÃ¨me de poids faible -EL, -mel ou -little Produire une sortie petit boutiste -EB, -meb ou -big Produire une sortie gros boutiste -mpic GÃ©nÃ©rer PIC -mno-fp-as-gp-relax Supprimer la relÃ¢che fp-as-gp pour ce fichier -mb2bb-relax Optimisation de sauts dos-Ã -dos -mno-all-relax Supprimer toutes les relÃ¢ches pour ce fichier -EL,-little produire du code et des donnÃ©es pour systÃ¨mes Ã octets de poids faible -I RÃ‰PERTOIRE ajouter le RÃ‰PERTOIRE Ã la liste de recherche des directives .include -Ip identique Ã -ignore-parallel-conflicts -J ne pas avertir lors d'un dÃ©bordement signÃ© -K avertir lorsque des diffÃ©rences sont altÃ©rÃ©es lors de longs dÃ©placements -KPIC gÃ©nÃ©rer PIC -L,--keep-locals conserver les symboles locaux (i.e. dÃ©butant par Â«Â LÂ Â») -M,--mri assembler en mode compatibilitÃ© MRI -N Avertir lorsque l'expansion des branches est faite pour des sauts. -O essayer d'optimiser le code. Implique -parallel -O1, Optimiser pour la performance -Os Optimiser pour l'espace -Q ignorÃ© -Q ignorÃ© -V afficher la version de l'assembleur -Q ignorÃ© -V afficher la version de l'assembleur -EB/-EL gÃ©nÃ©rer du code grand/petit boutien --32/--64 gÃ©nÃ©rer du code 32 ou 64 bits -Q ignorÃ© -V afficher la version de l'assembleur -k ignorÃ© -R joindre la section de donnÃ©es avec la section texte -V afficher la version de l'assembleur -Qy, -Qn ignorÃ© -W --no-warn supprimer les avertissements -Wnp identique Ã -no-warn-explicit-parallel-conflicts -Wnuh identique Ã -no-warn-unmatched-high -Wp identique Ã -warn-explicit-parallel-conflicts -Wuh identique Ã -warn-unmatched-high -X ignorÃ©e -Z gÃ©nÃ©rer le fichier objet mÃªme aprÃ¨s des erreurs -c avertir si un commentaire est trouvÃ© -f escamoter le prÃ©traitement des espaces et des commentaires -fixed-special-register-names Permettre seulement les noms originaux de registres spÃ©ciaux -g --gen-debug gÃ©nÃ©rer les informations de dÃ©bug -globalize-symbols Rendre tous les symboles globaux. -gnu-syntax Bloquer la compatibilitÃ© avec la syntaxe mmixal -h, -H Ne rien exÃ©cuter, afficher ce message d'aide. DÃ©prÃ©ciÃ©. -h-tick-hex Supporter les constantes hexadÃ©cimales dans le style H'00 -ignore-parallel-conflicts ne vÃ©rifie pas les instructions parallÃ¨les -linker-allocated-gregs S'il n'y a pas de dÃ©finition GREG pouvant convenir pour les opÃ©randes d'une instruction, laisser l'Ã©diteur de liens faire la rÃ©solution. -m%s%s -m32r dÃ©sactiver le support du jeu d'instructions m32rx -m32r2 supporter le jeu Ã©tendu d'instructions m32r2 -m32rx supporter le jeu Ã©tendu d'instructions m32rx -m4byte-align Marque le binaire comme utilisant un alignement 32 bits (dÃ©faut) -m8byte-align Marque le binaire comme utilisant un alignement 64 bits -mEA -mbarrel-shifter -mbarrel_shifter -mcrc -mdsp-packa -mdsp_packa -mdvbf -mld-extension-reg-mask -mlock -mmac-24 -mmac-d16 -mmac_24 -mmac_d16 -mmin-max -mmin_max -mmul64 -mno-mpy -mnorm -mrtsc -msimd -mswap -mswape -mtelephony -muser-mode-only -mxy -mN - ne pas insÃ©rer de NOP aprÃ¨s le changement d'interruptions (dÃ©faut) -mQ - activer la relaxation durant l'assemblage. DANGEREUX ! -mP - activer les instructions polymorphes -mY - ne pas avertir Ã propos de NOP manquants aprÃ¨s le changement d'interruptions -m[no-]%-17s Active/dÃ©sactive %s -march= DÃ©finir le type de machine H8300 Ã l'une de ces valeurs: h8300h, h8300hn, h8300s, h8300sn, h8300sx, h8300sxn -madd-bnd-prefix ajouter le prÃ©fix BND Ã tous les branchements valide -mall-ext Activer le support de toutes les extensions et instructions -mall-opcodes accepter tous les opcodes AVR, mÃªme non supportÃ©s par MCU -mno-skip-bug dÃ©sactiver les avertissements pour l'escamotage des instructions de 2 mots (par dÃ©faut pour avr4, avr5) -mno-wrap rejeter les instructions rjmp/rcall avec un bouclage Ã 8K (par dÃ©faut pour avr3, avr5) -mrmw accepter les instruction Lecture-Modification-Ã‰criture -mlink-relax gÃ©nÃ©rer les rÃ©adressages pour la relaxation du lieur -mno-link-relax ne pas gÃ©nÃ©rer de rÃ©adressages pour la relaxation du lieur. -mgcc-isr accepter la pseudo instruction __gcc_isr. -mamd64 accepter uniquement l'ISA AMD64 -march=ARCH activer les instructions de l'architecture ARCH -march=CPU[,+EXTENSION...] gÃ©nÃ©rer du code pour CPU et EXTENSION, CPU est l'un de ceux-ci: -march=ms1-16-002 autoriser les instructions ms1-16-002 (par dÃ©faut) -march=ms1-16-003 autoriser les instructions ms1-16-003 -march=ms1-64-001 autoriser les instructions ms1-64-001 -march=ms2 autoriser les instructions ms2 -mavxscalar=[128|256] encoder les instructions scalaires AVX avec une longueur de vecteur spÃ©cifique -mbig-endian gÃ©nÃ©rer du code pour architectures Ã octets de poids fort -mbig-obj gÃ©nÃ©rer des fichiers pour gros objets -mcpu= spÃ©cifie le nom du CPU cible -md - Forcer la copie de donnÃ©es de la ROM vers la RAM au dÃ©marrage -mdata-region={none|lower|upper|either} - sÃ©lectionner la rÃ©gion dans laquelle les donnÃ©es seront placÃ©es. -mdsbt le code utilise l'adressage DSBT -mevexlig=[128|256|512] encoder les instructions scalaires EVEX avec une longueur de vecteur spÃ©cifique -mevexrcig=[rne|rd|ru|rz] encoder les instructions EVEX avec la valeur spÃ©cifique EVEX.RC pour les instructions ignorÃ©es uniquement SAE -mevexwig=[0|1] encoder les instructions EVEX avec la valeur spÃ©cifique EVEX.W pour les instructions qui ignorent le bit EVEX.W -mextension activer le support des opcodes Ã©tendus -mfdpic assembler pour l'ABI FDPIC -mfence-as-lock-add=[no|yes] encoder lfence, mfence et sfence comme lock addl $0x0, (%%{re}sp) -mgcc-abi Marque le binaire comme utilisant l'ancienne ABI GCC -mhard-float Marque le binaire comme utilisant les insns FP (dÃ©faut pour e2v3 et suivants) -mindex-reg supporter les registres pseudo index -mintel64 accepter uniquement l'ISA Intel64 -mip2022 restreindre au insns IP2022 -mip2022ext supporter le jeu Ã©tendu d'instructions IP2022 -ml - activer le modÃ¨le de code large -mlittle-endian gÃ©nÃ©rer du code pour architectures Ã octets de poids faibles -mmnemonic=[att|intel] utiliser les mnÃ©moniques AT&T/Intel -mn - insÃ©rer un NOP aprÃ¨s le changement d'interruptions -mnaked-reg n'exige pas le prÃ©fixe Â«Â %%Â Â» pour les registres -mno-bcond17 dÃ©sactiver l'instruction b disp17 -mno-dsbt le code n'utilise pas l'adressage DSBT -mno-fdpic/-mnopic dÃ©sactiver -mfdpic -mno-pic l'adressage du code est dÃ©pendant de la position -mno-stld23 dÃ©sactiver les instructions st/ld offset23 -mold-gcc supporter les anciennes (<= 2.8.1) versions de gcc -momit-lock-prefix=[no|yes] retirer tous les prÃ©fixes de verrous -moperand-check=[none|error|warning] vÃ©rifier la validitÃ© des combinaisons des opÃ©randes -mpic l'adressage du code est indÃ©pendant de la position -mpid=far le code utilise un adressage des donnÃ©es indÃ©pendant de la position, les accÃ¨s GOT utilisent l'adressage DP lointain -mpid=near le code utilise un adressage des donnÃ©es indÃ©pendant de la position, les accÃ¨s GOT utilisent l'adressage DP proche -mpid=no le code utilise un adressage des donnÃ©es dÃ©pendant de la position -mrelax permettre la relÃ¢che -mrelax permettre la relÃ¢che -mrelax-relocations=[no|yes] gÃ©nÃ©rer des rÃ©adressages relaxÃ©es -mrh850-abi Marque le binaire comme utilisant l'ABI RH850 (dÃ©faut) -mshared dÃ©sactiver l'optimisation de branche pour du code partagÃ© -msilicon-errata=[,â€¦] - activer les correctifs pour les erratas du silicium -msilicon-errata-warn=[,â€¦] - avertir quand un correctif pourrait Ãªtre nÃ©cessaire noms d'erratas supportÃ©s: cpu4, cpu8, cpu11, cpu12, cpu13, cpu19 -msoft-float Marque le binaire comme n'utilisant pas les insns FP (dÃ©faut pour prÃ©-e2v3) -msse-check=[none|error|warning] vÃ©rifier les instructions SSE -msse2avx encoder les instructions SSE avec le prÃ©fixe VEX -msyntax=[att|intel] utiliser la syntaxe AT&T/Intel -mtune=CPU optimiser pour CPU, CPU est l'un de ceux-ci: -mv850 le code vise le v850 -mv850e le code vise le v850e -mv850e1 le code vise le v850e1 -mv850e2 le code vise le v850e2 -mv850e2v3 le code vise le v850e2v3 -mv850e2v4 Alias pour -mv850e3v5 -mv850e3v5 Le code cible le v850e3v5 -mwarn-signed-overflow avertir lors de dÃ©bordements des valeurs signÃ©es immÃ©diates -mwarn-unsigned-overflow avertir s'il y a dÃ©bordement des valeurs immÃ©diates non signÃ©es -my - avertir Ã propos de NOP manquants aprÃ¨s le changement d'interruptions -n ne pas optimiser l'alignement du code -q ne pas produire d'avertissement -nIp identique Ã -no-ignore-parallel-conflicts -no-bitinst refuser les instructions de champ de bits Ã©tendues du M32R2 -no-expand Ne pas faire l'expansion de GETA, branchements, PUSHJ ou JUMP en de multiples instructions. -no-ignore-parallel-conflicts vÃ©rifie les instructions parallÃ¨les pour -no-merge-gregs Ne pas faire la fusion des dÃ©finitions GREG avec des valeurs proches. -no-pad-sections ne pas remplir la fin des sections jusqu'Ã une frontiÃ¨re d'alignement -no-parallel dÃ©sactive -parallel -no-predefined-syms Ne pas fournir de constantes internes mmixal. Implique -fixed-special-register-names. -no-warn-explicit-parallel-conflicts ne pas avertir lorsque des instructions -no-warn-unmatched-high ne pas avertir lorsque des rÃ©adressages bas sont manquants -nocpp ignorÃ©e -nosched dÃ©sactiver les restrictions de planification -o NOM nommer le fichier d'objets de sortie NOM (par dÃ©faut a.out) -parallÃ¨le essayer de combiner les instructions en parallÃ¨le -relax CrÃ©er du code relaxable pour l'Ã©diteur de liens -s ignorÃ© -w ignorÃ©e -warn-explicit-parallel-conflicts avertir lorsque des instructions parallÃ¨les -warn-unmatched-high avertir lorsqu'il y a un rÃ©adressage de type haut qui ne concorde pas avec un rÃ©adressage de type bas -x Ne pas avertir quand on ne sait pas si une opÃ©rande avec GETA, un branchement, PUSHJ ou JUMP n'est pas Ã l'intÃ©rieur de la gamme. L'Ã©diteur de liens interceptera les erreurs. Cela implique -linker-allocated-gregs. -xauto enlever automatiquement les violations de dÃ©pendances (par dÃ©faut) -xnone aucune vÃ©rification des violations de dÃ©pendances -xdebug passer en mode dÃ©bug le vÃ©rificateur de violations de dÃ©pendances -xdebugn dÃ©bug du vÃ©rificateur des violations des dÃ©pendances mais dÃ©sactive la vÃ©rification des violations de dÃ©pendances -xdebugx dÃ©bug du vÃ©rificateur des violations des dÃ©pendances et active @FICHIER lire les options dans le FICHIER %s; *input_line_pointer == Â«Â %cÂ Â» 0x%02x Options en assembleur spÃ©cifiques Ã AArch64Â : Options en assembleur spÃ©cifiques ARM: Options en assembleur spÃ©cifiques Blackfin: Options spÃ©cifiques de la ligne de commande FR30: Version de l'assembleur GNU %s (%s) utilisant la version BFD %s.Options en assembleur spÃ©cifiques H8300: Options spÃ©cifiques M32R de la ligne de commande: Options spÃ©cifiques M32R de la ligne de commande: Options de la ligne de commande spÃ©cifiques Ã MMIX: Options de la ligne de commande spÃ©cifiques MetaÂ : Options spÃ©cifiques RL78 de la ligne de commande: Options spÃ©cifiques RX de la ligne de commande: Options spÃ©cifiques de l'assembleur Score: Options V850: Options de la ligne de commande spÃ©cifiques Ã XC16X: Options de la ligne de commande spÃ©cifiques Ã XSTORMY16: Options Z8K: -z8001 gÃ©nÃ©rer le code segmentÃ© -z8002 gÃ©nÃ©rer le code non segmentÃ© -linkrelax crÃ©er du code de relÃ¢che pour l'Ã©dition de liens rÃ©adressage de branchement tronquÃ© (0x%x) [-2^9 ~ 2^9-1] rÃ©adressage de branchement tronquÃ© (0x%x) [-2^19 ~ 2^19-1] rÃ©adressage de branchement tronquÃ© (0x%x) [-2^9 ~ 2^9-1]!%s n'utilise pas un numÃ©ro de sÃ©quencerÃ©adressage !samgp vers le symbole sans .prologue: %sÂ«Â %dÂ Â» (instance d'un nombre %d d'une Ã©tiquette %s)Â«Â .elseÂ Â» sans Â«Â .ifÂ Â» correspondantÂ«Â .elseifÂ Â» aprÃ¨s Â«Â .elseÂ Â»Â«Â .elseifÂ Â» sans Â«Â .ifÂ Â» correspondantÂ«Â .endifÂ Â» sans Â«Â .ifÂ Â»# Exemple d'instructions Â«Â %sÂ Â» .sect .text _start: # registre bars# conflit de longueur#4 n'est pas valide sur H8/300.###$DPR_BYTE n'est pas supportÃ© dans ce contexte$DPR_GOT n'est pas supportÃ© dans ce contexte$DPR_HWORD n'est pas supportÃ© dans ce contexte$DPR_WORD n'est pas supportÃ© dans ce contexte$DSBT_INDEX doit Ãªtre utilisÃ© avec __c6xabi_DSBT_BASE$DSBT_INDEX n'est pas supportÃ© dans ce contexte$GOT n'est pas supportÃ© dans ce contexte$PCR_OFFSET n'est pas supportÃ© dans ce contexte$dbg et $depc sont dÃ©sactivÃ©s quand DEBUG est Ã©teint$hi et $lo sont dÃ©sactivÃ©s quand MUL et DIV sont Ã©teints$mb0, $me0, $mb1 et $me1 sont dÃ©sactivÃ©s quand COP est Ã©teintopÃ©rateur % a besoin d'une expression absolue%%%s() doit Ãªtre le terme le plus Ã l'extÃ©rieur de l'expression%%hi16/%%lo16 s'applique uniquement Ã .short ou .hword%%hi8 s'applique uniquement Ã .byte%d erreur%d erreurs%d avertissement%d avertissements%s %s -- Â«Â %sÂ Â»%s -- dÃ©claration Â«Â %sÂ Â» ignorÃ©e%s NOP insÃ©rÃ©%s Â«Â %sÂ Â» a dÃ©jÃ un alias Â«Â %sÂ Â»%s l'argument doit Ãªtre une chaÃ®ne de caractÃ¨res%s Ã l'opÃ©rande %d â€” Â«Â %sÂ Â»Directive %s sans nom%s pour Â«Â %sÂ Â»%s pour l'instruction Â«Â %sÂ Â»l'instruction %s n'accepte pas le suffixe .b%s instruction, l'opÃ©rande %d ne correspond pas%s est activÃ© par le fanion vle%s n'est pas utilisÃ© pour la cible sÃ©lectionnÃ©e%s ne peut pas occuper la plage de dÃ©lai d'une autre instruction de branchement.%s doit Ãªtre %d Ã l'opÃ©rande %d â€” Â«Â %sÂ Â»%s doit avoir une valeur constante%s n'est pas dÃ©sactivÃ© par le fanion vle%s n'est pas supportÃ© en mode MIPS16offset %2$d de %1$s hors limiteoffset %s %d hors des limites %d Ã %d%s hors du domaine (%d n'est pas un multiple de %d)%s hors des limites %d Ã %d dans l'opÃ©rande %d â€” Â«Â %sÂ Â»%s hors limite (%d n'est pas entre %d et %d)%s hors limite (0x%s n'est pas entre 0x%s et 0x%s)registre %s identique Ã la base de rÃ©Ã©criturerÃ©adressages %s n'entre pas dans %d octetrÃ©adressages %s n'entre pas dans %d octetsLes rÃ©adressages %s n'entrent pas dans %u octetLes rÃ©adressages %s n'entrent pas dans %u octets%s requiert la valeur 0-2 comme opÃ©rande 1le deuxiÃ¨me argument de %s ne peut pas Ãªtre un nombre nÃ©gatif %d%s rÃ©duit Ã %srÃ©cursion de symboles %s stoppÃ©e Ã la seconde apparition de Â«Â %sÂ Â»%s n'est pas supportÃ©e%s non supportÃ© comme correctif d'instruction%s sans %s%s, %s, gÃ©nÃ©ration d'un fichier objet erronÃ© %s, traitement des avertissements comme des erreurs%s: tentative de faire tourner le registre PC%s: symboles globaux non supportÃ©s dans les sections communes%s: pas de telle section%s: la sortie de la 1Ã¨re instruction est la mÃªme que l'entrÃ©e de la 2Ã¨me instruction - est-ce intentionnel ?%s: la sortie de la 2Ã¨me instruction est la mÃªme que l'entrÃ©e de la 1Ã¨re instruction - est-ce intentionnel ?%s: temps total d'assemblage: %ld.%06ld %s: type de fonction inattendu: %d%s: nom de processeur non reconnu%s: fermerait la boucle weakref: %s%s:%u: retour erronÃ© de bfd_install_relocation: %xrÃ©adressage %u octets ne peut pas Ãªtre appliquÃ© sur un champ de %u octetsÂ«Â %.*sÂ Â» instruction pas au dÃ©but du paquet d'exÃ©cutionÂ«Â %.*sÂ Â» instruction pas dans une boucle pipelinÃ©e par le logicielÂ«Â %.*sÂ Â» instruction pas supportÃ©e sur cette architectureÂ«Â %.*sÂ Â» instruction pas supportÃ©e sur cette unitÃ© fonctionnelleÂ«Â %.*sÂ Â» instruction pas supportÃ©e sur cette unitÃ© fonctionnelle pour cette architectureÂ«Â %sÂ Â» ne peut pas Ãªtre une weak_definition (actuellement uniquement supportÃ© dans les sections de type coalescÃ©)Â«Â %sÂ Â» ne peut Ãªtre une weak_definition (puisqu'il est dÃ©fini)Â«Â %sÂ Â» n'est pas rÃ©pÃ©table. Comportement rÃ©sultant est indÃ©fini.Â«Â %sÂ Â» est uniquement disponible dans DD2.0 ou supÃ©rieur.Â«Â %sÂ Â» ne peut Ãªtre empaquetÃ© avec d'autres instructions.Â«Â %sÂ Â» prÃ©cÃ©demment dÃ©clarÃ© comme Â«Â %sÂ Â».Â«Â %sÂ Â»: seule l'instruction NOP peut Ãªtre utilisÃ©e en parallÃ¨le sur le m32r')' requisÂ«Â ,Â Â» attenduÂ«Â APSRÂ Â», Â«Â CPSRÂ Â» ou Â«Â SPSRÂ Â» attendusÂ«Â ASRÂ Â» requismodificateur Â«Â HÂ Â» uniquement valable pour des registres accumulateursle modificateur Â«Â LÂ Â» n'est pas valable pour cette instructionÂ«Â LSLÂ Â» ou Â«Â ASRÂ Â» requisÂ«Â LSLÂ Â» requis'MFC_RdTagMask' (canal 12) est uniquement disponible dans DD2.0 ou supÃ©rieur.les fanions Â«Â PÂ Â», Â«Â NÂ Â» ou Â«Â ZÂ Â» ne peuvent Ãªtre spÃ©cifiÃ© que lors d'une accumulationle dÃ©calage Â«Â RORÂ Â» n'est pas permis'SPU_RdEventMask' (canal 11) est uniquement disponible dans DD2.0 ou supÃ©rieur.Â«Â [Â Â» attenduÂ«Â [Â Â» attendu aprÃ¨s la mnÃ©monique PLDÂ«Â [Â Â» attendu aprÃ¨s la mnÃ©monique PLIÂ«Â ]Â Â» attenduÂ«Â d.%sÂ Â» doit Ãªtre alignÃ© sur 8 octetsÂ«Â entry_numÂ Â» doit Ãªtre un nombre absolu dans [0,31]Â«Â ||Â Â» aprÃ¨s le prÃ©dicatÂ«Â ||Â Â» n'est pas suivi par une instructionÂ«Â ||^Â Â» sans SPMASK prÃ©cÃ©dentÂ«Â }Â Â» attendu Ã la fin du champ Â«Â optionÂ Â»(PC)+ imprÃ©visible(Requiert %s; architecture requise est %s.)(plt) est seulement valable dans des cibles de branchements(raison inconnue)*-%s en conflit avec d'autres options d'architecture, lequel implique -%s-(PC) imprÃ©visible-- chaÃ®ne non terminÃ©e-abi=[32|64] dÃ©finir la taille de l'expansion des opÃ©randes SHmedia et des types de fichiers objets -shcompact-const-crange gÃ©nÃ©rer des descripteurs de gamme du code pour les constantes dans les sections de code SHcompact -no-mix ne pas permettre le code SHMedia dans la mÃªme section que les constantes et le code SHcompact -no-expand ne pas faire l'expansion des instructions MOVI, PT, PTA ou PTB -expand-pt32 avec -abi=64, faire l'expansion des instructions PT, PTA et PTB pour le 32 bits seulement l'option --absolute-literals n'est pas supportÃ©e dans cette configuration Xtensa--compress-debug-sections=%s n'est pas supportÃ©l'option --density est ignorÃ©e--fdpic gÃ©nÃ©rer un fichier objet FDPIC --generics est dÃ©prÃ©ciÃ©; utilisez plutÃ´t --transform--gstabs n'est pas supportÃ© pour ia64--hash-size requiert un argument numÃ©rique--isa=[shmedia dÃ©finir le jeu d'instructions par dÃ©faut du SH64 | SHmedia | shcompact | SHcompact] l'option --no-density est ignorÃ©e--no-generics est dÃ©prÃ©ciÃ©; utilisez plutÃ´t --no-transform--no-relax est dÃ©prÃ©ciÃ©; utilisez plutÃ´t --no-transform--no-underscore est invalide pour une format a.out--nops requiert un argument numÃ©rique--pic est invalide pour ce format d'objet--relax est dÃ©prÃ©ciÃ©; utilisez plutÃ´t --transform-32 crÃ©er un fichier objet de 32 bits -64 crÃ©er un fichier objet de 64 bits -32 crÃ©er un fichier objet pour l'ABI o32 (par dÃ©faut) -n32 crÃ©er un fichier objet pour l'ABI on32 -64 crÃ©er un fichier objet pour l'ABI 64 -EL gÃ©nÃ©rer du code pour machine Ã octets de poids faible -EB gÃ©nÃ©rer du code pour machine Ã octets de poids fort --little-endian-data gÃ©nÃ©rer du code pour machine ayant des instructions Ã octets de poids fort et des donnÃ©es Ã octets de poids faible -G ne peut pas Ãªtre utilisÃ© dans du code indÃ©pendant de la position-G ne peut Ãªtre utilisÃ© avec du code PIC SVR4-G ne peut pas Ãªtre utilisÃ© avec abicalls-G n Place donnÃ©es <= n octets dans la zone des petites donnÃ©es -G n'est pas supportÃ© dans cette configuration-KPIC gÃ©nÃ©rer PIC -V afficher la version de l'assembleur -undeclared-regs ignorer l'utilisation d'un registre global Ã l'application sans la directive .register (par dÃ©faut) -no-undeclared-regs forcer les erreurs lors de l'utilisation d'un registre global Ã l'application sans directive .register appropriÃ©e --dcti-couples-detect avertir lorsqu'un couple DCTI imprÃ©visible est trouvÃ© -q ignorÃ© -Qy, -Qn ignorÃ© -s ignorÃ© -KPIC, -call_shared gÃ©nÃ©rer du code SVR4 indÃ©pendant de la position -call_nonpic gÃ©nÃ©rer du code non-PIC qui peut fonctionner avec des DSO -mvxworks-pic gÃ©nÃ©rer du code VxWorks indÃ©pendant de la position -non_shared ne pas gÃ©nÃ©rer du code qui peut fonctionner avec des DSO -xgot supposer une GOT 32 bits -mpdr, -mno-pdr activer/dÃ©sactiver la crÃ©ation de sections .pdr -mshared, -mno-shared dÃ©sactiver/activer l'optimisation .cpload pour du code (non partagÃ©) indÃ©pendant de la position -mabi=ABI crÃ©er un fichier objet conforme Ã l'ABI pour: L'option -R n'est pas supportÃ©e pour cette cible.-TSO utiliser le Total Store Ordering -PSO utiliser le Partial Store Ordering -RMO utiliser le Relaxed Memory Ordering -expand-pt32 invalid en mÃªme temps que -no-expand-expand-pt32 seulement valide avec -abi=64-k gÃ©nÃ©rer en PIC -l utiliser 1 mot pour les rÃ©fÃ©rences de symboles non dÃ©finis [2 par dÃ©faut] -pic, -k gÃ©nÃ©rer du code indÃ©pendant de la position -S convertir jbsr en jsr --pcrel ne jamais convertir les branchements relatifs au PC en sauts absolus --register-prefix-optional reconnaÃ®tre les noms de registre sans caractÃ¨re de prÃ©fixe --bitwise-or ne pas traiter Â«Â |Â Â» comme un caractÃ¨re de commentaire --base-size-default-16 registre de base sans taille est 16 bits --base-size-default-32 registre de base sans taille est 32 bits (par dÃ©faut) --disp-size-default-16 dÃ©placement avec une taille inconnue est 16 bits --disp-size-default-32 dÃ©placement avec une taille inconnue est 32 bits (par dÃ©faut) -mCPU Ã©quivalent Ã -march=CPU -mtune=CPU. DÃ©prÃ©ciÃ©. -no-mCPU ne pas gÃ©nÃ©rer de code spÃ©cifique au CPU. Pour -mCPU et -no-mCPU, CPU doit Ãªtre un des suivants: -mPIC Marquer le fichier gÃ©nÃ©rÃ© comme utilisant du grand code indÃ©pendant de la position -m[no-]%-16s active/dÃ©sactive l'extension de l'architecture %s -maltivec gÃ©nÃ©rer du code pour AltiVec -mvsx gÃ©nÃ©rer du code pour les instructions Vector-Scalar (VSX) -me300 gÃ©nÃ©rer du code pour la famille PowerPC e300 -me500, -me500x2 gÃ©nÃ©rer du code pour Motorola e500 core complex -me500mc, gÃ©nÃ©rer du code pour Freescale e500mc core complex -me500mc64, gÃ©nÃ©rer du code pour Freescale e500mc64 core complex -me5500 gÃ©nÃ©rer du code pour Freescale e5500 core complex -me6500, gÃ©nÃ©rer du code pour Freescale e6500 core complex -mspe gÃ©nÃ©rer du code pour les instructions Motorola SPE -mspe2 gÃ©nÃ©rer du code pour les instructions SPE2 Freescale -mvle gÃ©nÃ©rer du code pour les instructions VLE Freescale -mtitan gÃ©nÃ©rer du code pour AppliedMicro Titan core complex -mregnames autoriser des noms symboliques pour les registres -mno-regnames interdire les noms symboliques pour les registres -march=%s n'est pas compatible avec l'ABI sÃ©lectionnÃ©e-march= sÃ©lection l'architecture -mcpu= sÃ©lectionne le cpu [%s par dÃ©faut] -mcpu= spÃ©cifier la version du CPU -mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat} -mdouble Marque le fichier gÃ©nÃ©rÃ© comme utilisant les instructions FP double prÃ©cision -mdsp gÃ©nÃ©rer des instructions DSP -mno-dsp ne pas gÃ©nÃ©rer d'instruction DSP -mdspr2 gÃ©nÃ©rer des instructions DSR R2 -mno-dspr2 ne pas gÃ©nÃ©rer d'instruction DSP R2 -mdspr3 gÃ©nÃ©rer des instructions DSR R3 -mno-dspr3 ne pas gÃ©nÃ©rer d'instruction DSP R3 -mdword Marquer le fichier comme utilisant un alignement de pile de 8 octets -me rediriger les erreurs vers le fichier -merrors-to-file -mfar-mode | -mf utiliser un adressage Ã©tendu -mfdpic Assemble pour l'ABI FDPIC -mfix-loongson2f-jump correctif pour les instructions JUMP Loongson2F -mfix-loongson2f-nop correctif pour l'errata NOP Loongson2F -mfix-vr4120 correctif pour certains errata VR4120 -mfix-vr4130 correctif d'errata mflo/mfhi VR4130 -mfix-24k insÃ©rer un nop aprÃ¨s les instructions ERET et DERET -mfix-cn63xxp1 correctif pour l'errata PREF CN63XXP1 -mgp32 utiliser des GPR 32 bits, indÃ©pendamment de l'ISA choisi -mfp32 utiliser des FPR 32 bits, indÃ©pendamment de l'ISA choisi -msym32 supposer que tous les symboles on des valeurs 32 bits -O0 supprimer les NOP superflus, n'Ã©change pas les branchements -O supprimer les NOP superflus et Ã©change les branchements --trap, --no-break capturer les exceptions de division par 0 et les dÃ©bordement de multiplication --break, --no-trap interrompt les exceptions de division par 0 et les dÃ©bordement de multiplication -mfpr-32 Marque le fichier gÃ©nÃ©rÃ© comme n'utilisant que 32 FPR -mfpr-64 Marque le fichier gÃ©nÃ©rÃ© comme utilisant les 64 FPR -mgpr-32 Marque le fichier gÃ©nÃ©rÃ© comme n'utilisant que 32 GPR -mgpr-64 Marque le fichier gÃ©nÃ©rÃ© comme utilisant les 64 GPR -mhard-float autoriser les instructions en virgule flottante -msoft-float ne pas autoriser les instructions en virgule flottante -msingle-float autoriser uniquement les opÃ©rations en virgule flottante 32 bits -mdouble-float autoriser les opÃ©rations en virgule flottante 32 bits et 64 bits --[no-]construct-floats autorise [ou non] la construction de valeurs en virgule flottante --[no-]relax-branch autoriser [ou non] la relÃ¢che des sauts hors limite --mignore-branch-isa accepter les branches invalides qui requiÃ¨rent un changement de mode ISA -mno-ignore-branch-isa rejeter les branches invalides qui requiÃ¨rent un changement de mode ISA -mnan=ENCODAGE choisir une convention d'encodage NaN IEEE 754 parmiÂ : -minsn32 ne gÃ©nÃ©rer que des instructions microMIPS 32 bits -mno-insn32 gÃ©nÃ©rer toutes les instruction microMIPS -mips1 gÃ©nÃ©rer des instructions MIPS ISA I -mips2 gÃ©nÃ©rer des instructions MIPS ISA II -mips3 gÃ©nÃ©rer des instructions MIPS ISA III -mips4 gÃ©nÃ©rer des instructions MIPS ISA IV -mips5 gÃ©nÃ©rer des instructions MIPS ISA V -mips32 gÃ©nÃ©rer des instructions MIPS32 ISA -mips32r2 gÃ©nÃ©rer des instructions MIPS32 version 2 ISA -mips32r3 gÃ©nÃ©rer des instructions MIPS32 version 3 ISA -mips32r5 gÃ©nÃ©rer des instructions MIPS32 version 5 ISA -mips32r6 gÃ©nÃ©rer des instructions MIPS32 version 6 ISA -mips64 gÃ©nÃ©rer des instructions MIPS64 ISA -mips64r2 gÃ©nÃ©rer des instructions MIPS64 version 2 ISA -mips64r3 gÃ©nÃ©rer des instructions MIPS64 version 3 ISA -mips64r5 gÃ©nÃ©rer des instructions MIPS64 version 5 ISA -mips64r6 gÃ©nÃ©rer des instructions MIPS64 version 6 ISA -march=CPU/-mtune=CPU gÃ©nÃ©rer du code/planification pour le CPU, oÃ¹ CPU prend Ãªtre: -mips16 gÃ©nÃ©rer des instructions mips16 -no-mips16 ne pas gÃ©nÃ©rer d'instruction mips16 -mips16 ne peut Ãªtre combinÃ© avec -micromips-mlibrary-pic Marquer le fichier gÃ©nÃ©rÃ© comme utilisant du code indÃ©pendant de la position pour des librairies -mmcu gÃ©nÃ©rer des instructions MCU -mno-mcu ne pas gÃ©nÃ©rer d'instruction MCU -mmedia Marque le fichier gÃ©nÃ©rÃ© comme utilisant les instructions media -mmicromips gÃ©nÃ©rer des instructions microMIPS -mno-micromips ne pas gÃ©nÃ©rer d'instruction microMIPS -mmicromips ne peut Ãªtre combinÃ© avec -mips16-mmsa gÃ©nÃ©rer des instruction MSA -mno-msa ne pas gÃ©nÃ©rer d'instruction MSA -mmt gÃ©nÃ©rer des instructions MT -mno-mt ne pas gÃ©nÃ©rer d'instruction MT -mmuladd Marquer le fichier gÃ©nÃ©rÃ© comme utilisant des instructions add/subtract multiples -mno-dword Marquer le fichier comme utilisant un alignement de pile de 4 octets -mno-pack Ne pas autoriser le compactage des instructions -mnopic DÃ©sactive -mpic, -mPIC, -mlibrary-pic et -mfdpic -mpack Autorise le compactage des instructions -mpic Marquer le fichier gÃ©nÃ©rÃ© comme utilisant du petit code indÃ©pendant de la position -mppc64, -m620 gÃ©nÃ©rer le code pour PowerPC 620/625/630 -mppc64bridge gÃ©nÃ©rer le code pour PowerPC 64, incluant le pont insns -mbooke gÃ©nÃ©rer le code pour 32-bit PowerPC BookE -ma2 gÃ©nÃ©rer le code pour l'architecture A2 -mpower4, -mpwr4 gÃ©nÃ©rer le code pour l'architecture Power4 -mpower5, -mpwr5, -mpwr5x gÃ©nÃ©rer le code pour l'architecture Power5 -mpower6, -mpwr6 gÃ©nÃ©rer le code pour l'architecture Power6 -mpower7, -mpwr7 gÃ©nÃ©rer le code pour l'architecture Power7 -mpower8, -mpwr8 gÃ©nÃ©rer le code pour l'architecture Power8 -mpower9, -mpwr9 gÃ©nÃ©rer le code pour l'architecture Power9 -mcell gÃ©nÃ©rer le code pour l'architecture Cell Broadband Engine -mcom gÃ©nÃ©rer le code pour les instructions communes Power/PowerPC -many gÃ©nÃ©rer le code pour n'importe quelle architecture (PWR/PWRX/PPC) -mrelocatable support pour l'option GCC -mrelocatble -mrelocatable-lib support pour l'option GCC -mrelocatble-lib -memb initialiser le bit PPC_EMB dans les fanions ELF -mlittle, -mlittle-endian, -le gÃ©nÃ©rer le code pour systÃ¨me Ã octets de poids faible -mbig, -mbig-endian, -be gÃ©nÃ©rer le code pour systÃ¨me Ã octets de poids fort -msolaris gÃ©nÃ©rer le code pour Solaris -mno-solaris ne pas gÃ©nÃ©rer le code pour Solaris -K PIC activer EF_PPC_RELOCATABLE_LIB dans les fanions ELF -V afficher la version de l'assembleur -Qy, -Qn ignorÃ© -msmartmips gÃ©nÃ©rer des instructions smartmips -mno-smartmips ne pas gÃ©nÃ©rer d'instruction smartmips -msoft-float Marque le fichier gÃ©nÃ©rÃ© comme utilisant la virgule flottante logicielle -mtomcat-debug Arrangements de dÃ©bug pour tomcat -mtomcat-stats Afficher les statistiques pour les arrangements pour tomcat -mvirt gÃ©nÃ©rer des instructions de virtualisation -mno-virt ne pas gÃ©nÃ©rer des instructions de virtualisation -mxpa gÃ©nÃ©rer des instructions eXtended Physical Address (XPA) -mno-xpa ne pas gÃ©nÃ©rer d'instructions eXtended Physical Address (XPA) -no-expand valide seulement avec SHcompact ou SHmedia-no-mix est invalide sans spÃ©cification de SHcompact ou SHmedia-nops=num si plus que num nops sont nÃ©cessaires pour un alignement, utiliser un branchement -ppc476-workaround avertir si Ã©met des donnÃ©es vers des sections de code -shcompact-const-crange est invalide sans SHcompact.%s en dehors de %s...longueur de .COMMon (%d.) < 0 ! IgnorÃ©.longueur de .COMMon (%ld.) <0! IgnorÃ©.longueur de .COMMon (%lu) hors limite, ignorÃ©.EQU doit utiliser une Ã©tiquette.EXIT doit apparaÃ®tre Ã l'intÃ©rieur d'une procÃ©dureExpression .REG doit Ãªtre un registre.REG doit utiliser une Ã©tiquettelongueur .SCOMMon (%ld.) <0! IgnorÃ©.l'expression .abiversion n'est pas Ã©valuÃ©e en une constante.abort dÃ©tectÃ©. Abandon..arch requiert une option --march=... correspondantele pseudo-op .asmfunc n'est disponible qu'avec le fanion -mccs..asmfunc rÃ©pÃ©tÃ©..asmfunc sans fonction..begin [no-]density est ignorÃ©Directive .begin sans concordance de directive .endDirective .begin sans directive .ent prÃ©cÃ©denteDirective .begin sans directive .file prÃ©cÃ©dentele littÃ©ral .begin est dÃ©prÃ©ciÃ©; utilisez plutÃ´t .literal.begin/.bend dans diffÃ©rents segmentsla directive .bend nomme un symbole inconnuDirective .bend sans directive .ent prÃ©cÃ©denteDirective .bend sans directive .file prÃ©cÃ©dentetaille .bss %d < 0 !taille .bss %ld < 0 !argument taille manquant dans .bss alignement de .bundle_align_mode trop grand (%u au maximum).bundle_lock n'a pas de sens sans .bundle_align_modela sÃ©quence .bundle_lock est Ã %u octets mais la limite de .bundle_align_mode est %u octetsla sÃ©quence .bundle_lock occupe %u octets mais la taille du paquet est seulement %u octets.bundle_lock sans .bundle_unlock correspondant.bundle_unlock sans .bundle_lock prÃ©cÃ©dent.callinfo n'est pas Ã l'intÃ©rieur de la dÃ©finition de procÃ©dure.cfi_endproc sans directive correspondante .cfi_startproc.cfi_fde_data n'est pas supportÃ© pour cette cible.cfi_fde_data sans .cfi_startproc correspondant.cfi_inline_lsda n'est pas supportÃ© pour cette cible.cfi_inline_lsda invalide pour cette trame.cfi_inline_lsda vu pour une trame sans .cfi_lsda.cfi_lsda exige des arguments d'encodage et de symbole.cfi_personality exige des arguments d'encodage et de symbole.cfi_personality_id n'est pas supportÃ© pour cette cibleil manque le langage et la version dans la directive .compileril manque la version dans la directive .compiler.cpload n'est pas dans la section Â«Â noreorderÂ Â»le pseudo-op .def n'est disponible qu'avec le fanion -mccs..def pseudo opÃ©rateur utilisÃ© Ã l'intÃ©rieur de .def/.endef: ignorÃ©.pseudo-op .def utilisÃ© en dehors de .def/.endef; ignorÃ©.dim pseudo opÃ©rateur utilisÃ© Ã l'extÃ©rieur de .def/.endef: ignorÃ©.pseudo-op .dim utilisÃ© en dehors de .def/.endef; ignorÃ©.ef n'est pas prÃ©cÃ©dÃ© de .function.end [no-]density est ignorÃ©Directive .end n'a pas de nomDirective .end manquante ou symbole inconnuDirective .end ne nomme pas le mÃªme symbole que .entdirective .end nomme un symbole inconnudirective .end sans directive .ent prÃ©cÃ©dentedirective .end n'est pas prÃ©cÃ©dÃ©e de la directive .ent.directive .end sans directive .file prÃ©cÃ©dentedirective .end sans concordance avec une directive .ent.end n'est pas dans la section de textesymbole .end n'a pas de correspondance avec le symbole .entsymbole .end n'a pas de correspondance avec le symbole .ent..end%c n'est pas prÃ©cÃ©dÃ© de %s.end%s n'est pas prÃ©cÃ©dÃ© de .%sle pseudo-op .endasmfunc n'est disponible qu'avec le fanion -mccs..endasmfunc sans .asmfunc..endasmfunc sans fonction.pseudo-op .endef utilisÃ© avant .def; ignorÃ©.endef pseudo opÃ©rateur utilisÃ© Ã l'extÃ©rieur de .def/.endef: ignorÃ©..endfunc manquant pour la dÃ©claration .func prÃ©cÃ©dente.endfunc manquant pour la dÃ©claration .proc prÃ©cÃ©denteLa directive .ent n'a pas de nomDirective .ent sans symboledirective .ent sans concordance avec une directive .end.ent ou .aent n'est pas dans la section texte.ent ou .aent n'est pas dans la section texte..err rencontrÃ©directive .error invoquÃ©e dans le fichier source.es n'est pas prÃ©cÃ©dÃ© de .bs.fail %ld rencontrÃ©compte .field Â«Â %dÂ Â» hors limite (1 <= X <= 32)taille de .fill limitÃ©e Ã %d.fmask en dehors de .entdirective .fnend sans .fnstart.frame Ã l'extÃ©rieur de .ent.gnu_attribute %d,%d est incompatible avec Â«Â %sÂ Â».gnu_attribute %d,%d n'est plus supportÃ©.gnu_attribute %d,%d n'est pas reconnu par l'ABI en virgule flottante.gnu_attribute %d,%d requiert Â«Â %sÂ Â»Directive .handler sans nom.ifeqs erreur de syntaxe.incbin a un compte Ã zÃ©ro, Â«Â %sÂ Â» est ignorÃ©opÃ©rande .inst.n trop grand. Utilisez plutÃ´t .inst.w.largecomm supportÃ© uniquement en mode 64 bits, .comm produit.linkonce n'est pas supportÃ© pour ce format de fichier objet.literal n'est pas permis Ã l'intÃ©rieur de la rÃ©gion .begin literal.literal_position Ã l'intÃ©rieur de la directive literal; ignorÃ©.ln pseudo opÃ©rateur Ã l'intÃ©rieur de .def/.endef: ignorÃ©..loc avant .file.loc Ã l'extÃ©rieur de .text.loc pseudo opÃ©rateur Ã l'intÃ©rieur de .def/.endef: ignorÃ©.l'expression .localentry de Â«Â %sÂ Â» n'est pas une constantel'expression .localentry de Â«Â %sÂ Â» n'est pas une puissance de 2 valablepseudo-op .longcall a Ã©tÃ© vu en dehors d'une relaxationpseudo-op .longjump a Ã©tÃ© en dehors d'une relaxation.ltorg dans la section %s est associÃ© Ã .using dans la section %s.ltorg sans .using prÃ©cÃ©dent dans la section %sdÃ©bordement de pile .machinedÃ©passement nÃ©gatif de la pile .machinedÃ©bordement de pile .machinemodedÃ©passement nÃ©gatif de la pile .machinemode.mask en dehors de .ent.mask/.fmask Ã l'extÃ©rieur de .ent.module n'est pas permis aprÃ¨s la gÃ©nÃ©ration du code.module utilisÃ© avec un symbole non reconnuÂ : %s Directive .name sans symboleDirective .name n'est pas dans la section .link.option pic%d n'est pas supportÃ©e.option pic%d n'est pas supportÃ©e en mode VxWorks PIC.option pop sans .option pushDirective .pdesc n'a pas de symbole d'entrÃ©eDirective .pdesc n'est pas dans la section .link.pdesc ne correspond pas au dernier .ent.pdesc a un mauvais symbole d'entrÃ©e.popsection sans .pushsection correspondant; ignorÃ©.previous sans .section correspondante; ignorÃ©le pseudo .profiler requiert au moins deux opÃ©randes.directive .prologue sans directive .ent prÃ©cÃ©dente.prologue Ã l'intÃ©rieur d'un prologue.ref Ã l'extÃ©rieur de .csectle pseudo-op .ref n'est disponible qu'avec le fanion -mccs..sblock peut uniquement Ãªtre utilisÃ© avec des sections initialisÃ©es.scl pseudo opÃ©rateur utilisÃ© Ã l'extÃ©rieur de .def/.endef: ignorÃ©.pseudo-op .scl utilisÃ© en dehors de .def/.endef; ignorÃ©.sect: nom de sous-section ignorÃ©.set pop sans .set pushsyntaxe erronÃ©e pour .set l'expression .size de %s n'est pas une constante.size pseudo opÃ©rateur utilisÃ© Ã l'extÃ©rieur de .def/.endef: ignorÃ©.pseudo-op .size utilisÃ© en dehors de .def/.endef; ignorÃ©.space ou .fill avec une valeur nÃ©gative, ignorÃ©.space compteur de rÃ©pÃ©tition est nÃ©gatif, ignorÃ©.space compteur de rÃ©pÃ©tition est zÃ©ro, ignorÃ©.space spÃ©cifie une valeur non absoluenombre de rÃ©pÃ©titions .space/.bes est nÃ©gatif, ignorÃ©nombre de rÃ©pÃ©titions .space/.bes est zÃ©ro, ignorÃ©.stab%c n'est pas supportÃ©.stab%c: champ de description '%x' trop grand, essayez un format de dÃ©bug diffÃ©rent.stab%c: ignore les autres champs non nuls.stab%c: virgule manquante.stabx de la classe de stockage stsym doit Ãªtre Ã l'intÃ©rieur de .bs/.es.syntax %s requiert l'option Â«Â --no-underscoreÂ Â».syntax %s requiert l'option Â«Â --underscoreÂ Â».tag pseudo opÃ©rateur utilisÃ© Ã l'extÃ©rieur de .def/.endef: ignorÃ©.pseudo-op .tag utilisÃ© en dehors de .def/.endef; ignorÃ©.tag requiert une Ã©tiquette de structure.tag cible Â«Â %sÂ Â» qui est indÃ©fini.tc n'est pas dans la section .toc.tc sans Ã©tiquette.type pseudo opÃ©rateur utilisÃ© Ã l'extÃ©rieur de .def/.endef: ignorÃ©.pseudo-op .type utilisÃ© en dehors de .def/.endef; ignorÃ©.unwind_save ne supporte pas ce type de registre.usect: fanion d'alignement non nul ignorÃ©Directive .usepv sans nomDirective .usepv sans type.uses ne rÃ©fÃ¨re pas Ã un symbole local dans la mÃªme sectionpseudo-op .uses a Ã©tÃ© vu hors de la relaxationla cible .uses ne rÃ©fÃ¨re pas Ã un symbole local dans la mÃªme section.using: expression de l'adresse de base illÃ©gale ou trop complexeexpression .val est trop complexe.val pseudo opÃ©rateur utilisÃ© Ã l'extÃ©rieur de .def/.endef: ignorÃ©.pseudo-op .val utilisÃ© en dehors de .def/.endef; ignorÃ©.var ne peut Ãªtre utilisÃ© qu'avec une dÃ©finition de macro.vframepsp n'a pas de sens, je suppose que c'est .vframesp qui Ã©tait prÃ©vu.vliw n'est pas disponible quand VLIW est dÃ©sactivÃ©.directive .warning invoquÃ©e dans le fichier source.word %s-%s+%s n'avait pas la bonne tailletraitement de la table des cas .word a Ã©chouÃ©: table trop grande0x%lx hors limite pour un dÃ©placement signÃ© de 32 bits0x%lx: Â«Â %sÂ Â» type = %ld, classe = %d, segment = %d registre scalaire SIMD 128 bits ou quadruple prÃ©cision flottant attenduregistre scalaire SIMD 16 bits ou demi prÃ©cision flottant attenduadresse 16 bits pas permise dans des instructions MPXexpression 16 bitssaut de 16 bits hors limiteRÃ©adressage 16 bits utilisÃ© sur un opÃ©rande 8 bitsvaleur immÃ©diate 3 bits hors limiteregistre scalaire SIMD 32 bits ou simple prÃ©cision flottant attenduadresse 32 bits pas permise dans des instructions MPX 64 bits.Branchement conditionnel 32 bits a Ã©tÃ© gÃ©nÃ©rÃ©mode 32 bits pas supportÃ© sur Â«Â %sÂ Â»x86_64 32 bits est uniquement supportÃ© avec ELFchamp de 5 bits doit Ãªtre absoluimmÃ©diate de 5 bits trop grandeDÃ©placement 6 bits hors limitevaleur immÃ©diate 6 bit hors limiteRÃ©adressage 62 bits n'est pas encore implÃ©mentÃ©registre scalaire SIMD 64 bits ou double prÃ©cision flottant attenduregistre entier 64 bits ou SP attendumode 64 bits pas supportÃ© sur Â«Â %sÂ Â»68040 et 68851 spÃ©cifiÃ©s; instructions mmu peuvent Ãªtre assemblÃ©es incorrectementregistre scalaire SIMD 8 bits attenduDÃ©placement 8 bits hors limitevaleur immÃ©diate 8 bits hors limiteRÃ©adressage 8 bits utilisÃ© sur un opÃ©rande 16 bits: Valeur immÃ©diate dans cbcond est hors limite.: L'instruction requiert que frs2 et frsd soient dans le mÃªme registre: l'opÃ©rande relatif au PC ne peut Ãªtre une constante: l'opÃ©rande TLS ne peut Ãªtre une constante: Il n'y a que 32 registres F; [0-31]: Il n'y a que 32 registres F simple prÃ©cision; [0-31]: Il n'y a que 64 registres F; [0-63]: nombre asr doit Ãªtre entre 0 et 31: immÃ©diat crypto doit Ãªtre entre 0 et 31: nom de registre ccr attendu : nom de registre pc attendu : nom de registre r0-r7 attendu: %asrN attendu: immÃ©diat crypto attendu: opÃ©rande immÃ©diat imm2 hors limites (0-3): expression ASI invalide: nom ASI invalide: numÃ©ro ASI invalide: nom cpreg invalide: masque d'expression membar invalide: masque de nom membar invalide: masque du numÃ©ro membar invalide: expression de fonction de prÃ©recherche invalide: nom de fonction de prÃ©recherche invalide: numÃ©ro de fonction de prÃ©recherche invalide: mode siam invalide pour l'expression: numÃ©ro du mode siam invalide: opÃ©rande imm2 non immÃ©diat: traitement de la macro, l'indicateur de l'opcode rÃ©el n'a pas Ã©tÃ© trouvÃ© dans la table de hachage: registre d'Ã©tat auxiliaire non reconnaissable: registre hyper privilÃ©giÃ© non reconnaissable: registre privilÃ©giÃ© non reconnaissable:b non permis; utilise par dÃ©faut :w:lower16: pas permis dans cette instruction: l'opÃ©rande a trop de bits:valeur opÃ©rande(%d) trop grande pour la contrainte:taille de contrainte de rÃ©adressage inconnu:upper16: pas permis dans cette instruction spÃ©cifie pour ABI SpÃ©cifier une version d'abi peut Ãªtre v1, v2, v2fp, v2fpp assembler pour l'ABI virgule flottante Assembler pour l'architecture peut Ãªtre v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s assembler pour l'architecture Assembler pour la ligne de base peut Ãªtre v2, v3, v3m assembler pour le CPU assembler pour l'architecture DSP assembler pour l'architecture FPU SpÃ©cifier la configuration FPU 0: registres 8 SP / 4 DP 1: registres 16 SP / 8 DP 2: registres 32 SP / 16 DP 3: registres 32 SP / 32 DP,X<Ã©tiquette> contrÃ´le l'insertion implicite d'instructions IT assembler pour la version eabi fanion ? de section ignorÃ© quand G est prÃ©sent@%s n'est pas un rÃ©adressage complexe.rÃ©adressage @%s n'est pas supportÃ© dans le format de sortie %d bits@tls ne peut pas Ãªtre utilisÃ© avec les opÃ©randes Â«Â %sÂ Â»@tls ne peut pas Ãªtre utilisÃ© dans le dernier opÃ©randeUn nombre grand/flottant ne peut pas Ãªtre utilisÃ© comme dÃ©placement: 0x%lx utilisÃ©Un dÃ©calage de branchement requiert un alignement 0 MOD 4Une instruction de saut avec un immÃ©diat long est dÃ©tectÃ©e Ã la fin de l'Ã©tiquette ZOL @%sUn paramÃ¨tre nommÃ© Â«Â %sÂ Â» existe dÃ©jÃ pour la macro Â«Â %sÂ Â»Un registre d'Ã©tat ou un nom de bit d'Ã©tat est requisA0.2,A0.3,A1.2,A1.3 requis pour un registre QUICKRoTAAARG -> rÃ©adressage de constante non traitÃ©: %dADD/SUB sp, sp #immADRADRL utilisÃ© pour un symbole qui n'est pas dÃ©fini dans le mÃªme fichierAR %d uniquement accessible par unitÃ© %cRegistre AR pas trouvÃ© dans une rÃ©fÃ©rence indirecteOptions en assembleur spÃ©cifiques ARC: registre ARM attendul'instruction fp16 scalaire du ARMv8.2 ne peut pas Ãªtre conditionnelle, le comportement est IMPRÃ‰VISIBLEExtension AUDIO ISAOptions assembleur AVRÂ : -mmcu=[nom-avr] choisi la variante de microcontrÃ´leur [nom-avr] peut ÃªtreÂ : avr1 - cÅ“ur AVR classique sans RAM donnÃ©es avr2 - cÅ“ur AVR classique avec jusqu'Ã 8K de mÃ©moire programme avr25 - cÅ“ur AVR classique avec jusqu'Ã 8K de mÃ©moire programme plus l'instruction MOVW avr3 - cÅ“ur AVR classique avec jusqu'Ã 64K de mÃ©moire programme avr31 - cÅ“ur AVR classique avec jusqu'Ã 128K de mÃ©moire programme avr35 - cÅ“ur AVR classique avec jusqu'Ã 64K de mÃ©moire programme plus l'instruction MOVW avr4 - cÅ“ur AVR amÃ©liorÃ© avec jusqu'Ã 8K de mÃ©moire programme avr5 - cÅ“ur AVR amÃ©liorÃ© avec jusqu'Ã 64K de mÃ©moire programme avr51 - cÅ“ur AVR amÃ©liorÃ© avec jusqu'Ã 128K de mÃ©moire programme avr6 - cÅ“ur AVR amÃ©liorÃ© avec jusqu'Ã 256K de mÃ©moire programme avrxmega2 - XMEGA, > 8K, < 64K FLASH, < 64K RAM avrxmega3 - XMEGA, RAM + FLASH < 64K, Flash visible en RAM avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM avrtiny - cÅ“ur AVR Tiny avec 16 registres gp Abandon parce que la dÃ©claration a "%s"Valeur absolue relative au PC dans le code de relaxation. Erreur d'assembleur.....Valeur absolue dans le code de relaxation. Erreur d'assembleur.....AccÃ¨s Ã Â«Â %sÂ Â» comme un objet de thread localAccÃ¨s Ã la fonction Â«Â %sÂ Â» comme un objet thread localAjout d'un symbole non rÃ©solu n'est pas sur une frontiÃ¨re de mot.Ajout d'un symbole non rÃ©solu n'est pas sur une frontiÃ¨re de mot.Mode d'adressage *+ARx n'est pas permis pour un mode d'adressage par registre Â«Â memory-mappedÂ Â». Comportement rÃ©sultant est indÃ©fini.Mode d'adressage *+ARx est en Ã©criture seulement. Le rÃ©sultat de la lecture est indÃ©fini.Adresse de l'opÃ©rande immÃ©diatMode d'adressage pas encore implÃ©mentÃ©.DÃ©bordement du .word (%#lx) signÃ© ajustÃ©Â : instruction Â«Â switchÂ Â» trop grande.A ajustÃ© le dÃ©bordement signÃ© de .word (%ld): option -statement trop grande.Alignement (%lu) trop grand: 15 assumÃ©.Alignement doit Ãªtre une puissance de 2Alignement nÃ©gatif: 0 assumÃ©Alignement nÃ©gatif: 0 est utilisÃ©.Alignement trop grand: %d assumÃ©Alignement trop grand: %d. assumÃ©Alignement trop grand: %d. est utilisÃ©.Options pour Alpha: -32addr traiter les adresses comme des valeurs de 32 bits -F manque de soutien des instructions en virgule flottante -mev4 | -mev45 | -mev5 | -mev56 | -mpca56 | -mev6 | -mev67 | -mev68 | -mall spÃ©cifier la variante d'architecture Alpha -m21064 | -m21066 | -m21164 | -m21164a | -m21164pc | -m21264 | -m 21264a | -m21264b ces variantes contiennent les opcodes PALcode Une instruction IMM ne devrait pas Ãªtre prÃ©sente dans le fichier .sUne utilisation illÃ©gale d'une plage de dÃ©lai est dÃ©tectÃ©e Ã la fin de l'Ã©tiquette ZOL @%sUne instruction a Ã©tÃ© Ã©tendue (%s)L'architecture ne concorde pas sur Â«Â %s %sÂ Â».Les variantes d'architecture sont:Argument de .vec_size devrait Ãªtre 4 ou 16, actuel: %d.Argument de .vec_size n'est pas une constante.L'argument Ã .BLOCK/.BLOCKZ doit Ãªtre compris entre 0 et 0x3fffffffArgument pour .even ignorÃ©Assembleur ne supporte pas encore PICMessages de l'assembleur: Au moins un argument PR attenduAu moins deux arguments PR attendusTentative de purger la macro inexistante Â«Â %sÂ Â»Tentative de placer un symbole commun dans l'ensemble %sTentative de placer le symbole indÃ©fini dans l'ensemble %sTentative de redÃ©finition de l'ensemble de registres Â«Â %sÂ Â»Nom d'attribut pas reconnu: %sDÃ©calage auto incrÃ©mentÃ©/dÃ©crÃ©mentÃ© Â«Â %ldÂ Â» est hors limite.Registre auxiliaire AR0--AR7 requis pour l'indirectionImmÃ©diat BALIGN n'est pas 0, 1, 2 ou 3 (%lu)BFD est dÃ©synchronisÃ© avec GAS, type de section bien connu Â«Â %sÂ Â» non traitÃ©BSPEC dÃ©jÃ actif. Imbrication non supportÃ©e.BSPEC sans ESPEC.longueur BSS (%d) < 0 ignorÃ©elongueur BSS (%d.) <0! IgnorÃ©.Expression BYTE n'est pas un nombre purexpression BYTE n'est pas dans les bornes 0..255Directive .fmask erronÃ©eDirective .frame erronÃ©e paramÃ¨tre 1./2.Directive .frame erronÃ©e paramÃ¨tre 3./4.Directive .mask erronÃ©eMauvaise directive .section: nÃ©cessite a,s,w,x,M,S,G,T dans la chaÃ®neVersion COFF erronÃ© Â«Â %sÂ Â»Version CPU erronÃ©e Â«Â %sÂ Â»Mauvais registre RA (%d) pour .fnameRegistre de base erronÃ©, utilise $%d.Appel erronÃ© de MD_ATOF()Appel erronÃ© Ã MD_NTOF()Appel erronÃ© Ã md_atof ()Appel erronÃ© Ã md_atof() - formats en virgule flottante ne sont pas supportÃ©sAppel erronÃ© Ã md_atof()Construction erronÃ©e d'adressage indirect %sMauvais dÃ©placement %d (exige 0--255) Mauvaise expression @%s + %s.Table de opcode erronÃ©e, bris d'assemblage.opcode-table-option erronÃ©, vÃ©rifiez dans le fichier ns32k-opcode.hMauvais opÃ©randeOpÃ©rande invalide pour une instruction de chargement (load): Â«Â %sÂ Â»OpÃ©rande erronÃ© pour une instruction de stockage: Â«Â %sÂ Â»Mauvaise valeur de l'opÃ©rande: %sMauvaise liste de paramÃ¨tres pour la macro Â«Â %sÂ Â»Mauvais nom de registreMauvais nom de registre %sGamme de registre erronÃ©eType de correctif de rÃ©adressage erronÃ© (%d)Type de rÃ©adressage erronÃ©: 0x%02xSegment erronÃ© (devrait Ãªtre absolu).Segment erronÃ© dans l'expression.NumÃ©ro de sÃ©quence erronÃ©: !%s!%sMauvais suffixe aprÃ¨s Â«Â :Â Â» utilisez {b|w|d} oÃ¹ d est le choix par dÃ©fautSuffixe erronÃ©, utilise d par dÃ©fautExpression d'adresse mal composÃ©eRegistres Â«Â BankedÂ Â» non disponibles pour cette architectureGrand nombre trop grandR2 Ã octets de poids fort n'est pas supportÃ©.Un grand nombre n'est pas permis dans un littÃ©ral Â«Â shortÂ Â». Mode immÃ©diat assumÃ©.Grand nombre trop grand pour le format %c; tronquÃ©Grand nombre trop grand pour un Â«Â longÂ Â»Champ de bits hors limiteLes deux arguments doivent Ãªtre des symboles de substitutionÃ€ la fois the_insn.HI et the_insn.LO sont initialisÃ©s : %sCrochets incorrects dans le champ de l'opÃ©randeBranchement sur une adresse non alignÃ©eAssemblage cassÃ©. Aucune tentative d'assemblage.Opcode erronÃ©: Â«Â %sÂ Â» Â«Â %sÂ Â» C0 - C15 attenduOptions de la ligne de commande spÃ©cifiques Ã C54x: instruction CFI utilisÃ©e sans Ãªtre prÃ©cÃ©dÃ© de .cfi_startprocCFI n'est pas supportÃ© pour cette ciblerÃ©cupÃ©ration de l'Ã©tat CFI sans mÃ©morisation prÃ©cÃ©denteVersion de CPU a dÃ©jÃ Ã©tÃ© initialisÃ©CPU11: PC est la destination d'une instruction altÃ©rant SRCPU12: CMP/BIT avec une destination PC ignore l'instruction suivanteCPU13: SR est la destination d'une instruction altÃ©rant SRCPU19: Une instruction dÃ©finissant CPUOFF doit Ãªtre suivie d'un NOPCPU8: Pointeur de pile accÃ©dÃ© via un dÃ©calage impaireOptions spÃ©cifiques CRIS: symbole C_EFCN pour %s hors limiteAppel de gen_cond_branch_32 pour .arch common_v10_v32 Ne peut dÃ©placer %d octets par rÃ©adressage%sNe peut faire un rÃ©adressage PIC relatif au PC de %d octetsNe peut faire un rÃ©adressage relatif au PC de %d octetsNe peut faire un rÃ©adressage de %d octets relatif au PC pour le stockage de type %dNe peut faire un rÃ©adressage PIC de %d octetsNe peut faire un rÃ©adressage de %d octetsNe peut faire un rÃ©adressage de %d octets pour le stockage de type %dNe peut trouver la correspondance de l'indice de relaxation. Ligne: %dNe peut reprÃ©senter le rÃ©adressage %s dans ce format de fichier objetNe peut initialiser dlx_skip_hi16_flagNe peut ajouter le bit de stop pour marquer la fin du groupe d'instructionsNe peut changer les espace Ã l'intÃ©rieur d'une dÃ©finition de procÃ©dure. IgnorÃ©Ne peut modifier des sous-espaces Ã l'intÃ©rieur de la dÃ©finition d'une procÃ©dure. IgnorÃ©Ne peut traiter l'expression; utilise %ld par dÃ©fautNe peut utiliser un nombre flottant en litteral Â«Â shortÂ Â»: mode immÃ©diat utilisÃ©.Ne peut trouver l'opcode Ã faire concorder avec les opÃ©randesNe peut traiter O_big dans s390_exp_compareNe peut adresser par hachage %s: %sNe peut adresser par hachage Â«Â %sÂ Â»: %s Ne peut adresser par hachage l'instruction Â«Â %sÂ Â»:%sNe peut rediriger stderr vers le fichier Â«Â %sÂ Â»Ne peut relaxer la diffÃ©renceNe peut relocaliser l'expressionNe peut initialiser la valeur GPNe peut initialiser les masques de registresLes branchements longs ne sont pas disponibles sur cette architectureNe peut dÃ©couvrir la taille de l'opÃ©rande. Ne peut allouer un descripteur unwind Ne peut assembler l'instructionNe peut dÃ©finir un symbole d'exportation: %s Ne peut dÃ©finir le symbole statique: %s Ne peut exprimer le rÃ©adressage %s%d%sNe peut trouver le type de rÃ©adressage pour le symbole %s, code %dNe peut gÃ©nÃ©rer un type de rÃ©adressage pour le symbole %s, code %sNe peut traiter le correctifNe peut faire un rÃ©adressage %s relative au PCNe peut reprÃ©senter le rÃ©adressage Â«Â %sÂ Â» dans le fichier objetNe peut reprÃ©senter l'exposant sur %d bitsNe peut reprÃ©senter le type de rÃ©adressage %sPOPM ne peut Ãªtre utilisÃ© pour rÃ©tablir le registre SRUn registre spÃ©cial ne peut pas Ãªtre utilisÃ© avec cette instructionCasse valeur %ld inattendue Ã la ligne %d du fichier Â«Â %sÂ Â» Changement de version de CPU Ã la volÃ©e n'est pas supportÃ©Le changement Ã la volÃ©e de la gÃ©nÃ©ration du processeur n'est pas supportÃ©...Valeur GP choisie: %lx Accolade fermante manquanteVirgule et symbole attendus pour Â«Â .asg CHAÃŽNE, SYMBOLEÂ Â»Virgule et symbole attendus pour '.eval EXPR, SYMBOLE'Virgule attendueVirgule attendue Virgule attendue aprÃ¨s le nom de sectionLa valeur sur la ligne de commande Ã©crase la directive Â«Â .cpuÂ Â»Alignement nÃ©gative du commun; 0 est assumÃ©Alignement du commun n'est pas une puissance de 2Expression complexe pas supportÃ©eOpÃ©rande cible LAPC compliquÃ© n'est pas un multiple de deux. Utilisez LAPC.DCondition Â«Â %sÂ Â» ne concorde pas avec le groupe prÃ©cÃ©dentCondition Â«Â %sÂ Â» utilise un accumulateur diffÃ©rent de la condition prÃ©cÃ©denteCondition <%c%c> dans la directive de contrÃ´le structurÃ©e ne peut Ãªtre encodÃ©e correctementExpression constante %d hors des limites [%d, %d].Conversion du BSR relatif au PC en un JSR absoluConversion du branchement relatif au PC en un saut absoluConversion du branchement conditionnel relatif au PC en un saut absoluConversion du dÃ©placement relatif au PC en absoluCopyright Â© 2018 Free Software Foundation, Inc. Ne peut initialiser l'architecture et la machineN'a pu initialiser l'architecture et la machineN'a pu gÃ©nÃ©rer les opcodes des instructions d'extensionCrÃ©ation de sections avec .xdataN/.xrealN/.xstringZ est dÃ©prÃ©ciÃ©e.La section courante n'est pas initialisÃ©e, nom de section requis pour .clinkregistre D hors limite pour la version VFP choisieOptions D10V: -O Optimiser. Certaines opÃ©rations seront faites en parallÃ¨le. --gstabs-packing Empaqueter les instructions adjacentes short ensembles mÃªme lorsque --gstabs est spÃ©cifiÃ©. ActivÃ© par dÃ©faut. --no-gstabs-packing Si --gstabs est spÃ©cifiÃ©, ne pas empaqueter les instructions adjacentes ensembles. pointeur RAM DSP dans une unitÃ© incorrecteUtilisation simultanÃ©e de Â«Â f%dÂ Â» et Â«Â f%dÂ Â» est dangereuseCible par dÃ©faut Â«Â %sÂ Â» n'est pas supportÃ©e.Assembleur dÃ©fectueux. Aucune tentative d'assemblage.Branchement diffÃ©rÃ© pas disponible sur SH1Syntaxe dÃ©prÃ©ciÃ©e.Accumulateur de destination pour chaque partie de l'instruction parallÃ¨le doit Ãªtre diffÃ©rentRegistre de destination doit Ãªtre ARnLe registre de destination doit Ãªtre R0 ou R1Le registre de destination doit Ãªtre R2 ou R3Des diffÃ©rences de symboles dans des sections diffÃ©rentes ne sont pas supportÃ©esArguments diffÃ©rents trouvÃ©s pour .vec_size, prÃ©cÃ©dent %d, actuel %dValeur directe de %ld n'est pas convenableDirective .atmp uniquement disponible avec l'option -mintel-syntaxDirective .dual uniquement disponible avec l'option -mintel-syntaxDirective .enddual uniquement disponible avec l'option -mintel-syntaxDirective invalide Ã l'intÃ©rieur d'un paquetLa longueur de dÃ©placement %s est ignorÃ©e !DÃ©placement trop grand pour :dValeur de dÃ©placement %ld est trop grandeSupport des instructions de divisionsNe sait pas comment mesurer la largeur de %c dans md_assemble()Je ne sais pas comment gÃ©rer ce champ. %sJe ne sais pas comment relocaliser un opÃ©rande simple de type %sles instructions de produit scalaire ne peuvent pas Ãªtre conditionnelles, le comportement est IMPRÃ‰VISIBLEConditionnel %s dupliquÃ©Signe Ã©gal (=) en double dans l'instructionPrÃ©dicat de registre en double ignorÃ©Pseudo opcode %s en double.Les constantes EBCDIC ne sont pas supportÃ©es.DÃ©bug ECOFF dÃ©sactivÃ©.ENDLOOP sans LOOP correspondantoptions spÃ©cifiques EPIPHANY de la ligne de commande: ESPEC n'est pas prÃ©cÃ©dÃ© de BSPECArgument vide dans .endpArgument vide dans .procLe dÃ©compte des Ã©pilogues de %lu dÃ©passe le nombre de prologues imbriquÃ©s (%u)Registres de destination parallÃ¨le Ã©gaux, un rÃ©sultat sera abandonnÃ©Erreur %s dans %s Erreur dans l'argument %d. Attendu: Â«Â %sÂ Â»Erreur dans l'expressionErreur dans le traitement du rÃ©adressageErreur dans la syntaxe de la ligneErreur lors de l'initialisation des fanions de Â«Â %sÂ Â»: %sErreur: Nombre pair requis. Arrondi Ã %dExÃ©cuter %s dans IU en ordre sÃ©riel inverse peut ne pas fonctionnerExÃ©cution de %s dans IU peut ne pas fonctionnerExÃ©cution de %s dans IU peut ne pas fonctionner lors d'une exÃ©cution en parallÃ¨leExÃ©cuter %s en ordre sÃ©riel inverse avec %s peut ne pas fonctionneropcode Ã©tendu aprÃ¨s un branchement retardÃ©: Â«Â %sÂ Â»opcode Ã©tendu en mode dual: Â«Â %sÂ Â»Â«Â (Â Â» attenduÂ«Â )Â Â» attendueÂ«Â :Â Â» attenduÂ«Â [Â Â» attenduÂ«Â ]Â Â» attenduVirgule attendue aprÃ¨s la longueur du communVirgule attendue aprÃ¨s le nomVirgule attendue aprÃ¨s le nom Â«Â %sÂ Â»Virgule attendue aprÃ¨s un nom de symboleVirgule attendue aprÃ¨s le nom de symbole: reste de la ligne ignorÃ©.Expression immÃ©diate attendueChaÃ®ne entre apostrophes attendueRegistre attendu. Â«Â %sÂ Â» trouvÃ©.SÃ©parateur Â«Â =Â Â» attenduNombre simple attendu.Valeur constante attendueNom de registre attenduRegistre attendu.Un argument contenant une constante caractÃ¨re est attenduVirgule attendue aprÃ¨s le nom de l'errata du CPU, et non: %sOpÃ©rande attendu aprÃ¨s Â«Â ,Â Â»OpÃ©rande attendu aprÃ¨s Â«Â ,Â Â»; n'a rien trouvÃ©OpÃ©rande attendu avant Â«Â ,Â Â»; n'a rien trouvÃ©Registre D attendu en mode indexÃ© indirect.Second argument attenduLes arrÃªts explicites sont ignorÃ©s en mode autoErreur d'expression pour le modificateur d'opÃ©rande %%hi/%%lo L'expression Ã l'intÃ©rieur de %%%s n'a pu Ãªtre analysÃ©eExpression hors limite, utilise 0Expression trop complexe.Adressage Ã©tendu n'est pas supportÃ©e sur le CPU spÃ©cifiÃ©) superflueRebut superflu dans l'appel de fonction, Â«Â )Â Â» attenduRebut en trop sur la ligneFATAL: Attachement de l'en-tÃªte du compilateur %sFIRST n'est pas supportÃ© comme un argument pour .SUBSPACEbranchement FP dans une plage de dÃ©laibranchement FP prÃ©cÃ©dÃ© par une instruction FP; NOP insÃ©rÃ©FPA .unwind_save n'accepte pas une liste de registresregistre FPA attenduExtension FPU DPExtension FPU SPinstructions FPU fused-multiply-addParamÃ¨tre FRAME doit Ãªtre un multiple de 8: %d Options spÃ©cifiques FRV de la ligne de commande: Options FT32: Ã‰chec lors de la crÃ©ation de la section de propriÃ©tÃ©s Â«Â %sÂ Â» N'a pu trouver un mode valable pour Â«Â %sÂ Â».impossible de trouver le dÃ©but rÃ©el de la fonction: %s Erreur fatale: Champ incorrectement alignÃ© [%d] (%d).Champ hors limite [%d..%d] (%d).Fichier Â«Â %sÂ Â» n'est pas dans le format d'archive macroLe 1er opcode est long. Incapable de mÃ©langer des instructions tel que spÃ©cifiÃ©.Le premier opÃ©rande de .%s doit Ãªtre un prÃ©dicatLe premier opÃ©rande de .%s n'est pas un registreLe premier opÃ©rande de .%s n'est pas un registre valideLe premier opÃ©rande de .altrp n'est pas un registre de branchement valideLe premier opÃ©rande de .fframe doit Ãªtre une constanteLe premier opÃ©rande de .prologue doit Ãªtre une constante positive de 4 bitsLe premier opÃ©rande de .restore doit Ãªtre le pointeur de pile (sp)Le premier opÃ©rande de .save n'est pas un registreLe premier opÃ©rande de .save n'est pas un registre valideLe premier opÃ©rande de .save.b doit Ãªtre une constante positive de 5 bitsLe premier opÃ©rande de .save.g doit Ãªtre une constante positive de 4 bitsLe premier opÃ©rande de .save.gf doit Ãªtre une constante non nÃ©gative de 4 bitsLe premier opÃ©rande de .unwabi doit Ãªtre une constanteLe premier opÃ©rande de .vframe doit Ãªtre un registre gÃ©nÃ©ralCorrigez la dÃ©pendance des donnÃ©es: %s %s -- %s %s (insÃ©rez %d nop!/%d)Corrigez la dÃ©pendance des donnÃ©es: %s %s -- %s %s (insÃ©rez 1 pflush/%d)Correctif de %ld trop grand pour la largeur du champ de %dFlottant AC illÃ©gal en tant que opÃ©rande entierNombre en virgule flottante pas valable dans l'expressionRegistre en virgule flottante est dans la liste de registresForcÃ© le littÃ©ral Â«Â shortÂ Â» en mode immÃ©diat. now_seg=%s to_seg=%sA forcÃ© un dÃ©placement d'octetÂ«Â {Â Â» trouvÃ©e aprÃ¨s un passage explicite en mode automatiqueÂ«Â {Â Â» trouvÃ© alors que le paquetage est dÃ©jÃ commencÃ©Â«Â {Â Â» trouvÃ© alors que le paquetage manuel est dÃ©jÃ activÃ©Â«Â }Â Â» trouvÃ©e alors que le paquetage manuel est dÃ©sactivÃ©Â«Â }Â Â» trouvÃ© en dehors du tout paquetage.Utilisation d'un nom de registre non canonique %s; utilise %s Ã la place.Options coprocesseur Freescale XGATEÂ : -mshort utiliser l'ABI int de 16 bits (par dÃ©faut) -mlong utiliser l'ABI int de 32 bits -mshort-double utiliser l'ABI double de 32 bits -mlong-double utiliser l'ABI double de 64 bits (par dÃ©faut) --mxgate spÃ©cifier la variante du processeur [%s par dÃ©faut] --print-insn-syntax afficher la syntaxe de l'instruction en cas d'erreur --print-opcodes afficher la liste des instructions avec la syntaxe --generate-example gÃ©nÃ©rer un exemple de chaque instructionLa fonction espÃ¨re deux argumentsAssembleur GNU %s Version de l'assembleur GNU %s (%s) utilisant la version BFD %s GOT est dÃ©jÃ dans la table de symbolesGOT est dÃ©jÃ dans la table des symbolesmauvaise expression GOT avec %staille du prologue GP excÃ¨de la taille du champ, utilise 0 Ã la placeexpression GREG trop complexeRebut Ã la fin de l'instruction: Â«Â %sÂ Â».Ã‰chec de GAS, type de rÃ©adressage #%i Ã‰chec de GAS, type de rÃ©adressage %s Ã‰chec de GAS, valeur de rÃ©adressage %d Registre gÃ©nÃ©ral illÃ©gal en tant que opÃ©rande flottantLa section de groupe Â«Â %sÂ Â» n'a pas de signature de groupeLes registres HI/LO devraient Ãªtre spÃ©cifiÃ©s ensemblesLe registre HI/LO devraient Ãªtre spÃ©cifiÃ©s sans registre additionnelCapacitÃ© matÃ©rielle Â«Â %sÂ Â» pas activÃ©e pour Â«Â %sÂ Â»La fonction de hachage a retournÃ© Â«Â %sÂ Â».ADD, MOV, CMP sur registre haut utilisant le PCADD, MOV, CMP, BX, BLX sur registre haut utilisant le PCJe n'ai pas besoin ni n'utilise de fichier temporaire Â«Â %sÂ Â».Je n'utilise pas de fichier inter-passe ! -V ignorÃ©Options I960: Options IA-64: --mconstant-gp indiquer que le fichier utilise le modÃ¨le de constantes GP (initialiser le fanion d'en-tÃªte ELF EF_IA_64_CONS_GP) --mauto-pic indiquer que le fichier utilise le modÃ¨le de constantes GP sans les descripteurs de fonction (initialiser le fanion d'en-tÃªte ELF EF_IA_64_NOFUNCDESC_CONS_GP) -milp32|-milp64|-mlp64|-mp64 sÃ©lectionner le modÃ¨le de donnÃ©es (par dÃ©faut -mlp64) -mle | -mbe sÃ©lectionner le systÃ¨me Ã octet de poids faible ou fort (par dÃ©faut -mle) -mtune=[itanium1|itanium2] ajuster pour un CPU spÃ©cifique (par dÃ©faut -mtune=itanium2) -munwind-check=[warning|error] vÃ©rifie la directive unwind (par dÃ©faut -munwind-check=warning) -mint.b=[ok|warning|error] vÃ©rifie hint.b (par dÃ©faut -mhint.b=error) -x | -xexplicit activer la vÃ©rification des violations de dÃ©pendances la vÃ©rification des violations de dÃ©pendances options spÃ©cifiques IP2K de la ligne de commande: Les blocs IT contenant des instructions Thumb 16 bits des classes suivantes sont dÃ©prÃ©ciÃ©s avec ARMv8Â : %sLes blocs IT contenant des instructions Thumb 32 bits sont dÃ©prÃ©ciÃ©s avec ARMv8Les blocs IT contenant plus d'une instruction conditionnelle sont dÃ©prÃ©ciÃ©s dans ARMv8IT atterri dans la plage d'un bloc IT prÃ©cÃ©dentL'instruction IU ne peut pas Ãªtre laissÃ©e dans le conteneur de gaucheIgnore la tentative de redÃ©finition du symboleTentative ignorÃ©e de redÃ©finition du symbole Â«Â %sÂ Â»Tentative ignorÃ©e de redÃ©finition du symbole Â«Â %sÂ Â».Ignore la tentative de dÃ©border au delÃ de la fin de la rÃ©gionIgnore les changements des attributs de section pour %sDÃ©claration ignorÃ©e en raison de Â«Â %sÂ Â»Registre du processeur 32 bits illÃ©gal (Â«Â %sÂ Â») dans l'instruction: Â«Â %sÂ Â»Registre AR illÃ©gal dans une rÃ©fÃ©rence indirecteÃ‰chelle illÃ©gale - Â«Â %dÂ Â»ParamÃ¨tre Â«Â cinvÂ Â» illÃ©gal: Â«Â %cÂ Â»OpÃ©rande Â«Â mask16Â Â» illÃ©gal, l'opÃ©ration est non dÃ©finie - Â«Â %sÂ Â»Registre coprocesseur illÃ©gal dans l'instruction Â«Â %sÂ Â»Registre coprocesseur spÃ©cial illÃ©gal dans l'instruction Â«Â %sÂ Â»Combinaison illÃ©gale de fonctions de rÃ©adressageInstruction Ã©mulÃ©e illÃ©galePaire de registres d'index illÃ©gale (Â«Â %sÂ Â») dans l'instruction: Â«Â %sÂ Â»Instruction illÃ©gale ou opcode non implÃ©mentÃ©.OpÃ©rande illÃ©gal (arg %d)SÃ©parateur d'opÃ©rande Â«Â %cÂ Â» illÃ©galOpÃ©rande illÃ©gal.OpÃ©randes illÃ©gauxOpÃ©randes illÃ©gaux (espaces): Â«Â %sÂ Â»OpÃ©randes illÃ©gaux pour %sOpÃ©rande %s illÃ©galOpÃ©randes illÃ©gaux: %%%s ne peut Ãªtre utilisÃ©s seulement avec call __tls_get_addrOpÃ©randes illÃ©gaux: %%%s ne peut Ãªtre utilisÃ© ensemble avec d'autres rÃ©adressages dans insn ()OpÃ©randes illÃ©gaux: %%%s requiert des arguments dans ()OpÃ©randes illÃ©gaux: %%r_%s%d requiert des arguments dans ()OpÃ©randes illÃ©gaux: %%r_plt dans %d-octet de champ de donnÃ©esOpÃ©randes illÃ©gaux: %%r_tls_dtpoff dans %d-octet du champ de donnÃ©esOpÃ©randes illÃ©gaux: %%tls_ldo dans un champ de donnÃ©es de %d octetsOpÃ©randes illÃ©gaux: %%tls_ldo requiert des arguments dans ()OpÃ©randes illÃ©gaux: ne peut ajouter des expressions qui ne sont pas des constantes Ã %%%s()OpÃ©randes illÃ©gaux: ne peut faire de l'arithmÃ©tique impliquant %%%s() d'un symbole relocalisableOpÃ©randes illÃ©gaux: ne peut faire de l'arithmÃ©tique autre que + et - impliquant %%%s()OpÃ©randes illÃ©gaux: seulement %%r_%s%d permis dans %d-octets de champ de donnÃ©esOpÃ©randes illÃ©gaux: rebuts aprÃ¨s %%r_%s%d()OpÃ©randes illÃ©gaux: rebut aprÃ¨s %%tls_ldo()Registre processeur illÃ©gal (Â«Â %sÂ Â») dans l'instruction: Â«Â %sÂ Â»Registre illÃ©gal (Â«Â %sÂ Â») dans l'instruction: Â«Â %sÂ Â»Registre illÃ©gal (Â«Â %sÂ Â») dans l'instruction: Â«Â %sÂ Â»Registre illÃ©gal Â«Â %sÂ Â» dans l'instruction Â«Â %sÂ Â»Registre Â«Â %sÂ Â» illÃ©gal dans la liste des registres copRegistre Â«Â %sÂ Â» illÃ©gal dans la liste des registres cop spÃ©ciauxRegistre illÃ©gal Â«Â %sÂ Â» dans l'instruction Â«Â %sÂ Â»Registre Â«Â %sÂ Â» illÃ©gal dans la liste des registresRegistre Â«Â %sÂ Â» illÃ©gal dans la liste des registres utilisateursPaire de registres inconnue (Â«Â %sÂ Â») dans l'instruction: Â«Â %sÂ Â»Paire de registres illÃ©gale Â«Â %sÂ Â» dans l'instruction Â«Â %sÂ Â»Nom de section illÃ©gal Â«Â %sÂ Â» (provoque une collision des noms des sections unwind)Type d'opÃ©rande illÃ©gal (arg %d)L'opÃ©rande immÃ©diat n'est pas permis pour l'opÃ©rande %d.Valeur immÃ©diate %ld est trop grandeValeur immÃ©diate pour mbar > 32. Utilise Valeur immÃ©diate n'est pas dans les bornes de 16 bits: %ldValeur immÃ©diate n'est pas dans les bornes signÃ©es de 16 bits: %ldValeur immÃ©diate n'est pas dans les bornes non signÃ©es de 16 bits: %ldValeur immÃ©diate n'est pas dans les bornes non signÃ©es de 4 bits: %ldValeur immÃ©diate n'est pas dans les bornes non signÃ©es de 5 bits: %ldValeur immÃ©diate n'est pas dans les bornes non signÃ©es de 6 bits: %ldValeur immÃ©diate n'est pas dans les bornes non signÃ©es de 6 bits: %ldValeur immÃ©diate n'est pas dans les bornes de 8 bits: %ldValeur immÃ©diate n'est pas dans les bornes signÃ©es de 8 bits: %ldValeur immÃ©diate n'est pas dans les bornes non signÃ©es de 8 bits: %ldValeur immÃ©diate de %ld est trop grandeValeur immÃ©diate de %ld est trop grande pour ldfLes valeurs immÃ©diates %d et %d vont donner lieu Ã un comportement indÃ©fini.Adresse CSR inopportune (%lu)ImmÃ©diat CSRxI inopportun (%lu)Nombre de dÃ©calages erronÃ© (%lu)Utilisation inappropriÃ©e de OP1_IMM_IMPLIEDUtilisation inappropriÃ©e de OP1_MUST_BE_IMMPremier et second opÃ©rande incompatibles dans l'instructionValeur fr_opcode incorrecte dans frag. Erreur interne.....Nombre d'opÃ©randes incorrectNombre d'opÃ©randes incorrectSyntaxe incorrecte, %s.Valeur d'incrÃ©mentation/dÃ©crÃ©mentation est hors limite: Â«Â %ldÂ Â».L'index peut uniquement Ãªtre appliquÃ© aux registres rotatifs ou indirectsL'index doit Ãªtre un registre gÃ©nÃ©ralIndex hors de la gamme 0..%uRegistre d'index IR0,IR1 requis pour un dÃ©placementMode indexÃ© indirect n'est pas permis pour movb/movw.L'adressage indirect indexÃ© n'est pas valide pour 68HC11.L'index du registre indirect doit Ãªtre un registre gÃ©nÃ©ralBoucle infinie rencontrÃ©e lors du calcul des adresses des symboles de la section %sLes nombres infinis ne sont pas supportÃ©s par cette cible Info: Le .body initial doit prÃ©cÃ©der toute instructionLe .prologue initial doit prÃ©cÃ©der toute instructionL'insertion de Â«Â %sÂ Â» dans la table des types d'adresses a Ã©chouÃ©: %sInsertion de Â«Â %sÂ Â» dans la table de hachage des constantes a Ã©chouÃ©: %sInsertion de Â«Â %sÂ Â» dans la table d'indices a Ã©chouÃ©: %sL'insertion de Â«Â %sÂ Â» dans la table des registres a Ã©chouÃ©: %sInsertion de Â«Â %sÂ Â» dans la table de structure a Ã©chouÃ©: %sL'insn %s a une instruction de saut/branchement %s dans sa plage de dÃ©lai.L'insn %s a une instruction %s avec limm dans sa plage de dÃ©lai.Emplacement Insn pas mis dans l'enregistrement unwind.Instruction %s n'est pas permise dans la plage de dÃ©lai.L'instruction Â«Â %sÂ Â» n'est pas supportÃ©e dans la ligne de base.L'instruction %s requiert une expression absolueL'instruction Â«Â %sÂ Â» requiert une version LP de CPUL'instruction Â«Â %sÂ Â» requiert une mode d'adressage Ã©loignÃ©Instruction Â«Â %sÂ Â» n'est pas reconnue.L'instruction ne s'insÃ¨re pas dans les positions de dÃ©lais disponibles (insn %d-mots, %d position restante)L'instruction ne s'insÃ¨re pas dans les positions de dÃ©lais disponibles (insn %d-mots, %d positions restantes)L'instruction ne s'insÃ¨re pas dans les positions de dÃ©lai disponibles (insn %d-mots, %d position restante). Le comportement rÃ©sultant est indÃ©fini.L'instruction ne s'insÃ¨re pas dans les positions de dÃ©lai disponibles (insn %d-mots, %d positions restantes). Le comportement rÃ©sultant est indÃ©fini.L'instruction ne supporte par les adresses =NForme d'instruction pas supportÃ©e par cette architecture.Formats d'instruction pour Â«Â %sÂ Â»:Instruction dans le conteneur R est Ã©crasÃ©e par une instruction de contrÃ´le de flux du conteneur L.L'instruction doit Ãªtre exÃ©cutÃ©e en parallÃ¨leL'instruction doit Ãªtre exÃ©cutÃ©e en parallÃ¨le avec une autre.Instruction pas supportÃ©e par cette architectureL'instruction utilise une version avec long, aussi elle ne peut Ãªtre mÃ©langÃ©e tel que spÃ©cifiÃ©Les instructions n'utilisent pas de pipelines parallÃ¨les durant l'exÃ©cution.Les instructions ne peuvent pas Ãªtre exÃ©cutÃ©es en parallÃ¨leLes instructions partagent le mÃªme pipeline durant l'exÃ©cutionLes instructions utilisant des modificateurs de dÃ©calage long ou des adresses absolues ne sont pas rÃ©pÃ©tables. Comportement rÃ©sultant est indÃ©fini.Les instructions qui causent une discontinuitÃ© du PC ne sont pas permises dans une plage de dÃ©lai. Comportement rÃ©sultant est indÃ©fini.Intel K1OM supporte uniquement ELF 64 bitsLe K10M d'Intel est 64 bits uniquementIntel L1OM supporte uniquement ELF 64 bitsLe L10M d'Intel est 64 bits uniquementLe MCU Intel ne supporte pas l'architecture Â«Â %sÂ Â»Intel MCU supporte uniquement ELF 32 bitsLe MCU d'Intel est 32 bits uniquementErreur interne: ne peut adresser par hachage %s: %sErreur interne: ne peut repÃ©rer %s dans la table de hachageErreur interne: ne peut adresser par hachage %s: %sErreur interne: mauvaise longueur d'instructionErreur interne d'assembleur pour l'instruction %sErreur interne d'assembleur pour le format d'instruction %sErreur interne d'assembleur pour la macro %sProblÃ¨me interne. Essayer d'utiliser 0(r%d) au lieu de @r%dErreur de consistance interne. VÃ©rifier ns32k-opcode.hErreur interne (%s). Erreur interne Ã %s:%d. Erreur interne dÃ©couverte dans md_convert_frag: offset %ld. Merci de rapporter ceci.Erreur interne dans %s Ã %s:%d. Erreur interne: ne peut adresser par hachage %s: %sErreur interne: Erreur de plage. %sErreur interne: Erreur d'indice de relaxation. %s: %xErreur interne: incapable de repÃ©rer l'espace contenant pour %s.Erreur interne: Type de correctif %d inconnu (Â«Â %sÂ Â»)Erreur interne: ne peut trouver l'opcode Â«Â %sÂ Â» pour Â«Â %sÂ Â» Erreur interne: ne peut adresser par hachage Â«Â %sÂ Â»: %s Erreur interne: je ne sais pas comment forcer %s Ã la fin du groupe d'instructionsErreur interne: perte du opcode Â«Â %sÂ Â» Â«Â %sÂ Â» Erreur de logique interne dans iif.iifP[].typeErreur de logique interne dans iif.iifP[n].typeErreur de logique interne. Ligne %d, fichier: Â«Â %sÂ Â»Erreur de logique interne. ligne %d, fichier Â«Â %sÂ Â»Option --compress-debug-sections invalide: Â«Â %sÂ Â»Option --elf-stt-common= invalide: Â«Â %sÂ Â»Option --size-check= invalide: Â«Â %sÂ Â»Argument .CALL invalide: %sArgument Ã .CALLINFO invalide: %sArgument .SPACE invalideargument .SUBSPACE invalideFormat .insn invalide Condition d'addition invalide: %sCondition d'addition et de branchement invalideBranchement invalide sur la condition de bit: %cIdentificateur COPR invalideValeur de l'opÃ©rande CST4 invalide (arg %d)Condition comparaison et de branchement invalideCondition comparaison/soustraction invalideCondition comparaison/soustraction invalide: %sValeur de l'opÃ©rande DISPU4 invalide (arg %d)Expression d'Ã©tiquette de donnÃ©es invalideCondition de comparaison FP invalide: %sFormat d'opÃ©rande FP invalide: %3sComplÃ¨teur FTEST invalide: %sFormat d'opÃ©rande en virgule flottante invalide.Syntaxe de complÃ¨teur de chargement indexÃ© invalide.ComplÃ¨teur de chargement indexÃ© invalide.Condition d'instruction logique invalide.Nullification invalide: (%c)Expresion PIC invalideIdentificateur SFU invalideCondition dÃ©calage/extraction/dÃ©pÃ´t invalide.ComplÃ¨teur Load/Store courts invalide.ComplÃ¨teur Store Bytes Short invalideCondition d'instruction unaire (Unit) invalide.Registre accumulateur invalide.argument invalide %d pour .prologueDescription invalide de l'argument: %dPosition d'argument invalide: %s Argument invalide Ã l'option --abi: %sArgument invalide Ã l'option --isa: %sArgument invalide Ã l'option --match: %sArgument invalide vers .abi: %sArgument invalide pour .mode: %sRegistre auxiliaire invalide (utiliser AR0-AR7)CaractÃ¨re %s invalide avant l'opÃ©rande %sCaractÃ¨re %s invalide dans l'opÃ©rande %sCaractÃ¨re %s invalide dans l'opcodeCombinaison invalide d'instructions dans le paquet.Combinaison invalide: --abi=32 avec --abi=64Combinaison invalide: --abi=64 avec --abi=32Combinaison invalide: --abi=64 avec --isa=SHcompactCombinaison invalide: --isa=SHcompact avec --abi=64Combinaison invalide: --isa=SHcompact avec --isa=SHmediaCombinaison invalide: --isa=SHmedia avec --isa=SHcompactOpÃ©rande constant %s invalideArchitecture par dÃ©faut invalide, bris d'assemblage.Registre de destination invalide pour cette instruction, utiliser Â«Â tfrÂ Â».Registre de destination invalide.Directive invalideDÃ©placement invalide dans une rÃ©fÃ©rence indirecteSyntaxe dmad invalide Â«Â %sÂ Â»Utilisation redondante de Â«Â %c%dÂ Â» n'est pas permiseExpression invalide aprÃ¨s # numÃ©ro Expression invalide aprÃ¨s %%%% Expression invalideSÃ©lecteur de champ invalide. F%% assumÃ©.Taille de champ invalide, doit Ãªtre entre 1 et 32 inclus.Nombre en virgule flottante invalideOpÃ©rande d'Ã©criture immÃ©diat invalide.Mode indexÃ© indirect invalide.Registre d'index invalide, registre X attendu.Registre d'index invalide, registre Y attendu.Registre indexÃ© invalide.Mode d'adressage indirect invalideDÃ©placement %d invalide pour le mode d'adressage indirectInstruction %s erronÃ©eÃ‰tiquette invalide Â«Â %sÂ Â»ComplÃ¨teur de combinaisons left/right invalideLongueur invalide (utilisez 0 Ã %d)MnÃ©monique invalide Â«Â %sÂ Â»Mode invalide: %s Nombre invalideOpcode/opÃ©rande invalideOpÃ©rande invalide (s) pour une instruction parallÃ¨le Â«Â %sÂ Â»OpÃ©rande invalide (utilisez 1, 2, ou 3)opÃ©rande invalide dans l'expressionOpÃ©rande invalide pour Â«Â %sÂ Â»OpÃ©rande invalide: valeur immÃ©diate utilisÃ©e comme adresse.OpÃ©rande invalide: valeur immÃ©diate utilisÃ©e comme adresse de base.OpÃ©randes invalidesOpÃ©randes invalides %sOpÃ©randes invalides pour %sOpÃ©ration invalide sur le symboleOpÃ©rateur invalide pour l'opÃ©rande.Mode d'adresse invalide ou illÃ©gal combinÃ© avec un index-Ã©chelleRÃ©adressage relatif du PC invalideComplÃ¨teur de permutations invalideType d'enregistrement invalide pour le format P3.Type d'enregistrement invalide pour le format B1.Type d'enregistrement invalide pour le format P6.Type d'enregistrement invalide pour le format X1.Type d'enregistrement invalide pour le format X3.Registre invalide pour un instruction dbcc/tbcc.Registre invalide pour un post/prÃ© incrÃ©mentation.Registre invalide pour la simple prÃ©cision fmpyadd ou fmpysubRegistre invalide dans la liste des registresListe de registres invalide pour ldm/stm NumÃ©ro de registre invalide Ã Â«Â %.6sÂ Â»SpÃ©cification de registre invalide.Registre invalide.Registre invalide: Â«Â r%dÂ Â»Registre invalide: r0 et r15 illÃ©gauxRÃ©adressage invalideMode indexÃ©-Ã©chelle invalide, utilisez b, w, d ou qUtilisation simultanÃ©e de Â«Â f%dÂ Â» et Â«Â f%dÂ Â» n'est pas permiseRegistre source invalide pour cette instruction, utiliser Â«Â tfrÂ Â».Registre source invalide.Registre d'Ã©tat invalide Â«Â %sÂ Â»Indice invalide (utilisez 1 Ã %d)Suffixe invalide pour le bassin d'entrÃ©es littÃ©ralesSyntaxe invalide en mode d'adressage externeSyntaxe invalide dans le mode d'adressage relatif en mÃ©moireSyntaxe invalide en mode d'adressage relatif au PCUtilisation invalide de Â«Â %c%dÂ Â» en tant que opÃ©rande de sortieUtilisation invalide de Â«Â r%dÂ Â» en tant opÃ©rande de mise Ã jour de base de l'adresseUtilisation invalide de l'opÃ©rateur de parallÃ©lisation.JALX vers un symbole dans le mÃªme mode ISAInstruction de saut/branchement dÃ©tectÃ©e Ã la fin de l'Ã©tiquette ZOL @%sRebus aprÃ¨s Â«Â }Â Â»Â : Â«Â %sÂ Â»Rebut Ã la fin de la ligne, %s.Instruction noyau dÃ©tectÃ©e Ã la fin de l'Ã©tiquette ZOL @%sNoms MCU connusÂ :l'instruction LDP a besoin d'un opÃ©rande 24 bitsexpression LOC avec pas arriÃ¨re n'est pas supportÃ©eLOC vers une section inconnue ou indÃ©terminÃ©e lors de la premiÃ¨re passeLR et PC ne devraient pas Ãªtre tous les deux dans la liste des registresÃ‰tiquette "$%d" redÃ©finieL'Ã©tiquette Â«Â %sÂ Â» correspond Ã un nom de registre du processeurL'Ã©tiquette doit Ãªtre la premiÃ¨re dans un paquetÃ‰tiquette requise pour .tagSigne plus pas permis au dÃ©but d'une instruction coreLongueur de .comm Â«Â %sÂ Â» est dÃ©jÃ %ld. N'a pas Ã©tÃ© changÃ© en %d.Longueur de .comm Â«Â %sÂ Â» est dÃ©jÃ %ld. N'a pas Ã©tÃ© changÃ© pour %ld.Longueur de .lcomm Â«Â %sÂ Â» est dÃ©jÃ %ld. N'a pas Ã©tÃ© changÃ© Ã %ld.Longueur de .scomm Â«Â %sÂ Â» est dÃ©jÃ %ld. N'a pas Ã©tÃ© changÃ© Ã %ld.SpÃ©cification de longueur ignorÃ©e. Mode d'adressage 9F utilisÃ©Ligne %d: type de rÃ©adressage inconnu: 0x%x.Les numÃ©ros de lignes doivent Ãªtre des entiers positifs DÃ©bordement du bassin des littÃ©rauxChargements littÃ©rauxLes instructions longues ne peuvent pas Ãªtre combinÃ©es.Ressemble Ã une procÃ©dure, mais ne peut dire de quel genre. Bits du bas tronquÃ© dans l'opÃ©rande flottant immÃ©diatopcode spÃ©cifique M340 utilisÃ© lors de l'assemblage pour M210Options spÃ©cifiques MCORE: -{no-}jsri2bsr {dÃ©}sactiver la conversion jsri en bsr (par dÃ©faut: no) -{no-}sifilter {dÃ©}sactiver le comportement du filtre de silicon (par dÃ©faut: no) -cpu=[210|340] sÃ©lectionner le type de CPU -EB assembler pour un systÃ¨me Ã octets de poids fort (par dÃ©faut) -EL assembler pour un systÃ¨me Ã octets de poids faible l'option MCU requiert un nom la valeur MDRD doit Ãªtre entre 1 et 8Appel PIC MIPS Ã un registre autre que $25Options MIPS: -EB gÃ©nÃ©rer du code pour systÃ¨me Ã octets de poids fort -EL gÃ©nÃ©rer du code pour systÃ¨me Ã octets de poids faible -g, -g2 ne pas enlever les NOP inutiles ou les branchements de commutation (swap) -G NOMBRE permettre la rÃ©fÃ©rence des objets jusqu'Ã NOMBRE d'octets implicitement avec le registre GP [par dÃ©faut 8] Options MN10200: aucune pour l'instant Options assembleur MN10300: aucune pour l'instant opÃ©rande MOVI n'est pas une valeur signÃ©e de 32 bits: 0x%8x%08xpseudo-op MRI de style ORG n'est pas supportÃ©Options MSP430Â : -mmcu= - sÃ©lectionner le type de microcontrÃ´leur -mcpu={430|430x|430xv2} - sÃ©lectionner l'architecture du microcontrÃ´leur Options spÃ©cifiques de la ligne de commande MT: L'instruction MU ne peut pas Ãªtre dans le conteneur de droiteLa macro %s n'est pas encore implÃ©mentÃ©eMacro Â«Â %sÂ Â» a dÃ©jÃ Ã©tÃ© dÃ©finieregistre Maverick DSPSC attenduregistre Maverick MVAX attenduregistre Maverick MVD attenduregistre Maverick MVDX attenduregistre Maverick MVF attenduregistre Maverick MVFX attenduAu plus %d bits peuvent Ãªtre mis dans l'opÃ©rande Â«Â mask16Â Â»Options en ligne de commande spÃ©cifiques MeP: -EB assembler pour un systÃ¨me Ã poids fort -EL assembler pour un systÃ¨me Ã poids faible (dÃ©faut) -mconfig= spÃ©cifier une configuration de puce Ã utiliser -maverage -mno-average -mmult -mno-mult -mdiv -mno-div -mbitops -mno-bitops -mleadz -mno-leadz -mabsdiff -mno-absdiff -mminmax -mno-minmax -mclip -mno-clip -msatur -mno-satur -mcop32 active/dÃ©sactive les opcodes donnÃ©es Si -mconfig est donnÃ©, les autres options -m le modifie. Autrement, si aucune option -m n'est spÃ©cifiÃ©e, tous les opcodes centraux sont activÃ©s; toutes les options -m positives donnÃ©es sont les seules activÃ©es; toutes les options -m nÃ©gatives donnÃ©es sont les seules dÃ©sactivÃ©es; Registre de projection mÃ©moire Â«Â %sÂ Â» hors limiteInstructions 16 bits diverses.entry mal positionnÃ©. IgnorÃ©.Â«Â (Â Â» manquante aprÃ¨s la fonction de substitution de symboleÂ«Â )Â Â» manquanteÂ«Â )Â Â» manquant dans l'expression de symbole de substitution indicÃ©eÂ«Â ,Â Â» manquanteÂ«Â }Â Â» manquante Ã la fin du fichierÂ«Â }Â Â» manquanteÂ : Â«Â %sÂ Â») manquante) manquant dans ra(rb).EXIT manquant pour un .ENTRY.callinfo manquant.callinfo manquant pour cette procÃ©dure.callinfo manquant..endp manquant aprÃ¨s la dÃ©claration .proc prÃ©cÃ©dente.exit manquant .label_state %ld manquant.procend manquant Branchement manquant sur la condition de bitÂ«Â ]Â Â» manquant pour complÃ©ter le mode indexÃ©-indirect.Â«Â ]Â Â» manquant pour fermer l'opÃ©rande de registre indirect.Arguments manquants pour l'opcode Â«Â %sÂ Â».Terminateur de substitution forcÃ©e manquant Â«Â :Â Â»Nom de fonction manquant pour .PROCNom de fonction manquant pour .PROC (chaÃ®ne d'Ã©tiquette corrompue)Nom d'Ã©tiquette manquant pour .LABELNom de macro manquantCrochets pairÃ©s manquantes: Â«Â %sÂ Â»OpÃ©rande manquantOpÃ©rande manquant.Directive .using manquante ou mauvaisequalificateur de paramÃ¨tre manquant pour Â«Â %sÂ Â» dans la macro Â«Â %sÂ Â»Type de relation de prÃ©dicat manquantSecond registre manquant pour le mode indexÃ©-indirect.Second registre ou dÃ©calage pour le mode indexÃ©-indirect manquant.Nom de section manquantArgument pour la taille est manquantNom de symbole manquant dans la directiveValeur manquante pour le paramÃ¨tre requis Â«Â %sÂ Â» de la macro Â«Â %sÂ Â»MÃ©lange d'adressages normal et Ã©tendu n'est pas supportÃ©MÃ©lange des syntaxes de registres avec et sans Â«Â $Â Â».Plus d'un registre AR trouvÃ© dans une rÃ©fÃ©rence indirectePlus d'un dÃ©placement trouvÃ© dans une rÃ©fÃ©rence indirectePlus d'un opÃ©rateur de rÃ©adressage par insnOptions Motorola 68HC11/68HC12/68HCS12: -m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg spÃ©cifier le processeur [par dÃ©faut %s] -mshort utiliser l'ABI int de 16 bits (par dÃ©faut) -mlong utiliser l'ABI int de 32 bits -mshort-double utiliser l'ABI double de 32 bits -mlong-double utiliser l'ABI double de 64 bits (par dÃ©faut) --force-long-branches toujours convertir les branchements relatifs en absolus -S,--short-branches ne pas convertir les branchements relatifs en absolus lorsque le dÃ©calage est hors limite --strict-direct-mode ne pas convertir le mode direct en mode Ã©tendu lorsque l'instruction ne supporte pas le mode direct --print-insn-syntax afficher la syntaxe de l'instruction en cas d'erreur --print-opcodes afficher la liste des instruction avec la syntaxe --xgate-ramoffset dÃ©cale les adresses RAM de 0xc000 --generate-example gÃ©nÃ©rer un exemple de chaque instruction (utiliser en mode test) Plusieurs directives .cpu rencontrÃ©esSupport des instructions de multiplicationsDoit Ãªtre dans un espace avant de changer ou dÃ©clarer des sous-espaces. NOP insÃ©rÃ© entre deux instructions qui changent l'Ã©tat d'interruptionOptions NS32K: -m32032 | -m32532 sÃ©lectionner la variante d'architecture NS32K --disp-size-default=<1|2|4> NaNs ne sont pas supportÃ©s par cette cible Nom # Modes Min ops Max ops Modes masq. # UtilisÃ© Nan, utilise zÃ©ro.A besoin de #1 ou #2 iciregistre Neon en double ou quadruple prÃ©cision attenduregistre Neon en quadruple prÃ©cision attenduRegistre Neon en simple ou double prÃ©cision attenduProcÃ©dure imbriquÃ©esAucun !literal!%ld n'a Ã©tÃ© retrouvÃ©Aucun !tlsgd!%ld n'a Ã©tÃ© trouvÃ©Aucun !tlsldm!%ld n'a Ã©tÃ© trouvÃ©Pas de point d'entrÃ©e Â«Â balÂ Â» pour la procÃ©dure leafproc %sPas de .ENTRY pour ce .EXITPas d'addende autorisÃ© dans le rÃ©adressage @fptr()Pas de virgule aprÃ¨s .pdesc N'est pas compilÃ© pour le support de format de fichier objet de %d bitsPas de cadre actifPas d'instruction trouvÃ©ePas d'instruction ou opcode manquant.Aucun lda !gpdisp!%ld n'a Ã©tÃ© trouvÃ©Aucun ldah !gpdisp!%ld n'a Ã©tÃ© trouvÃ©Pas d'opÃ©rateurPas d'opÃ©rande de rÃ©adressagePas d'info de segment pour la section courantePas de telle entrÃ©e dans la liste. (registre cpu/mmu)Pas de tel opcodePas de symbole aprÃ¨s .code_addressPas de symbole aprÃ¨s .linkagePas d'opÃ©rande de rÃ©adressage d'Ã©tiquette valableSymbole non absolu: Â«Â %sÂ Â».Symboles non constant pas permis Symbole non global Â«Â %sÂ Â» ne peut Ãªtre une weak_definition.Pas une architecture coldfire dÃ©finiePas un type de fonctionPas une expression symboliquePas assez d'opÃ©randesN'est pas dans un espace. N'est pas dans un sous-espace. Le nombre d'Ã©lÃ©ments doit Ãªtre positifNombre trop grandOpÃ©rande immÃ©diate OPF est hors limite (0-0x1ff)Registre numÃ©rotÃ© impair utilisÃ© comme cible d'une instruction Ã registres multiplesDÃ©calage sur des structures imbriquÃ©s est ignorÃ©DÃ©calage hors des limites 16 bits pour movw/movb: %ldDÃ©calage hors limite en 16 bits: %ldDÃ©calage hors des limites 5 bits pour movw/movb: %ldDÃ©calage hors limite en 5 bits pour movw/movb: %ld.DÃ©calage hors des limites 9 bits pour movw/movb: %ldUne de ces instructions ne peut pas Ãªtre exÃ©cutÃ©e en parallÃ¨leSeuls des offsets constants sont supportÃ©sSeules les allocations Ã taille constante sont supportÃ©esUn seul pseudo opÃ©rateur .compiler par fichier !Un seul pseudo opÃ©rateur .copyright par fichier !Un seul pseudo opÃ©rateur .version par fichier !Seulement une comparaison conditionnelle est permiseSeulement un dÃ©bordement conditionnel est permisSeul le premier chemin oÃ¹ le conflit est rencontrÃ© est rapportÃ©Opcode %s pas disponible dans ce modeOpcode Â«Â %sÂ Â» n'est pas reconnu.Opcode Â«Â %sÂ Â» avec ces types d'opÃ©randes ne sont pas disponibles en mode %sOpcode Â«Â %sÂ Â» avec ces types d'opÃ©randes n'est pas disponible en mode H8/300Opcode Â«Â %sÂ Â» avec ces types d'opÃ©randes n'est pas disponible en mode H8/300HOpcode Â«Â %sÂ Â» avec ces types d'opÃ©randes n'est pas disponible en mode H8/300SOpcode(%d.%s): OpÃ©rande Â«Â %sÂ Â» est hors limite (utilisez 1 ou 2)L'opÃ©rande %d de .%s doit Ãªtre une constanteL'opÃ©rande %d de .%s doit Ãªtre un registre prÃ©servÃ©L'opÃ©rande %d de .%s doit Ãªtre un registre avec accÃ¨s en Ã©critureL'opÃ©rande %u de Â«Â %sÂ Â» devrait Ãªtre %sOpÃ©rande Â«Â %sÂ Â» est hors limite (%d <= x <= %d)OpÃ©rande Â«Â %xÂ Â» n'est pas reconnu dans fixup16.OpÃ©rande Â«Â %xÂ Â» n'est pas reconnu dans le fixup8.L'opÃ©rande a un dÃ©placement impair (arg %d)L'opÃ©rande n'est pas une constante. Â«Â %sÂ Â»OpÃ©randes ne concordent pasL'opÃ©rande de .vframe contredit le .prologueOpÃ©rande hors limite en 16 bits: Â«Â %ldÂ Â».OpÃ©rande hors limite en 8 bits: Â«Â %ldÂ Â».OpÃ©rande hors limite (arg %d)OpÃ©rande hors limite pour un branchement relatif: Â«Â %ldÂ Â»OpÃ©rande hors limite, %s.L'opÃ©rande de .copy_state doit Ãªtre une constanteL'opÃ©rande de .label_state doit Ãªtre une constanteL'opÃ©rande de .save.f doit Ãªtre une constante positive de 20 bitsL'opÃ©rande de .spill doit Ãªtre une constanteL'opÃ©rande de .vframesp doit Ãªtre une constante (offset relatif Ã sp)La valeur de l'opÃ©rande n'est pas dans les 64 ko supÃ©rieurs (arg %d)Les opÃ©randes de .save.gf ne peuvent pas Ãªtre tous les deux Ã zÃ©roL'opÃ©rateur peut uniquement Ãªtre appliquÃ© Ã des symboles.Option -b est dÃ©prÃ©ciÃ©e, veuillez utiliser -mbigOption -p est dÃ©prÃ©ciÃ©e, veuillez utiliser -mmemparmOption -r est dÃ©prÃ©ciÃ©e, veuillez utiliser -mregparmOption -s est dÃ©prÃ©ciÃ©e, veuillez utiliser -msmallL'option Â«Â %sÂ Â» n'est pas reconnue.Options: -a[sous-option...] activer l'affichage Sous-options [par dÃ©faut hls]: c omettre les faux conditionnels d omettre les directives de dÃ©bug g inclure les informations gÃ©nÃ©rales h inclure les sources de haut niveau l inclure l'assembleur m inclure l'expansion de macros n omettre le traitement des formulaires (forms) s inclure les symboles =FICHIER les lister dans le FICHIER (doit Ãªtre la derniÃ¨re sous-option) La gestion des offsets .word hors limite n'est pas implÃ©mentÃ©e pour .arch common_v10_v32DÃ©bordement dans l'expression, tronquÃ©e Ã 16 bitsDÃ©bordement dans l'expression, tronquÃ©e Ã 8 bitsÃ‰crasement de Tag_ARC_CPU_base dÃ©fini explicitementPC pas permis dans la liste des registresla partie PC de l'opÃ©rande est imprÃ©visibleBranchement relatif au PC vers le label %s qui n'est pas dans l'espace des instructionsrÃ©adressage relatif au PC pas permis pour le type (interne) %dPC utilisÃ© comme argument de RPTPC, CT, TR et TT sont traitÃ©s comme si ils Ã©taient une unitÃ© unique mais les opÃ©randes doivent Ãªtre dans des unitÃ©s diffÃ©rentesadresse relative au PC hors limiteaccÃ¨s relatif au PC vers une adresse mal alignÃ©e (%lx)accÃ¨s relatif au PC en utilisant un dÃ©calage mal alignÃ© (%lx)accÃ¨s relatif au PC en utilisant un symbole mal alignÃ©e (%lx)offset relatif au PC n'est pas alignÃ© sur 4 octetssaut relatif au PC hors limiterÃ©fÃ©rence relative au PC vers une section diffÃ©renterÃ©adressage relatif au PC doit Ãªtre rÃ©solu de maniÃ¨re trivialeDÃ©bordement du dÃ©calage du code PIC (max 16 bits signÃ©s)DÃ©bordement du dÃ©calage du code PIC (max 32 bits signÃ©s)la taille de rÃ©adressage PIC ne concorde pas avec la taille de l'opÃ©randeOptions PJ: -little gÃ©nÃ©rer du code pour systÃ¨me Ã octets de poids faible -big gÃ©nÃ©rer du code pour systÃ¨me Ã octets de poids fort Options PRU: -mlink-relax gÃ©nÃ©rer des rÃ©adressage pour la relaxation de l'Ã©diteur de liens (dÃ©faut). -mno-link-relax ne pas gÃ©nÃ©rer de rÃ©adressage pour la relaxation de l'Ã©diteur de liens. opÃ©rande PTA est un symbole SHcompactopÃ©rande PTB est un symbole SHmÃ©diaUn opcode parallÃ¨le ne peut pas contenir plus de deux instructionsLe paramÃ¨tre nommÃ© Â«Â %sÂ Â» n'existe pas pour la macro Â«Â %sÂ Â»ParamÃ¨tres de sous-espaces existants ne peuvent Ãªtre modifiÃ©sL'analyse a Ã©chouÃ©.Extension de performanceExtension de performance 2Peut-Ãªtre avez-vous mal orthographiÃ© %%tpoff() ?Instruction pipelinÃ©e: fsrc1 = fdestSVP rapporter cette anomalie. Veuillez utiliser --help pour connaÃ®tre les options pour cet assembleur. Valeur par dÃ©faut inutile pour le paramÃ¨tre requis Â«Â %sÂ Â» dans la macro Â«Â %sÂ Â»Utilisation inutile de p0 comme premier opÃ©rande de .%sUtilisation inutile de zÃ©ro premier opÃ©rande de .prologueMode post-dÃ©crÃ©ment n'est pas valide pour 68HC11.Mode post-incrÃ©ment n'est pas valide pour 68HC11.Options PowerPC: -a32 gÃ©nÃ©rer le code pour ELF32/XCOFF32 -a64 gÃ©nÃ©rer le code pour ELF64/XCOFF64 -u ignorÃ© -mpwrx, -mpwr2 gÃ©nÃ©rer le code pour POWER/2 (RIOS2) -mpwr gÃ©nÃ©rer le code pour POWER (RIOS1) -m601 gÃ©nÃ©rer le code pour PowerPC 601 -mppc, -mppc32, -m603, -m604 gÃ©nÃ©rer le code pour PowerPC 603/604 -m403 gÃ©nÃ©rer le code pour PowerPC 403 -m405 gÃ©nÃ©rer le code pour PowerPC 405 -m440 gÃ©nÃ©rer le code pour PowerPC 440 -m464 gÃ©nÃ©rer le code pour PowerPC 464 -m476 gÃ©nÃ©rer le code pour PowerPC 476 -m7400, -m7410, -m7450, -m7455 gÃ©nÃ©rer le code pour PowerPC 7400/7410/7450/7455 -m750cl gÃ©nÃ©rer le code pour PowerPC 750cl -m821, -m850, -m860 gÃ©nÃ©rer le code pour PowerPC 821/850/860 Mode prÃ©-incrÃ©ment n'est pas valide pour 68HC11Registre de prÃ©dicat attenduPrÃ©dicat source et cible requisPrÃ©fixe Â«Â d.Â Â» invalide pour l'instruction Â«Â %sÂ Â»Fin prÃ©maturÃ©e du suffixe -- Utilise d par dÃ©faut.save prÃ©cÃ©dent incompletLes variantes de processeur sont:Registre interdit utilisÃ© pour un registre rÃ©duit, %sLe pseudocode a dÃ©jÃ utilisÃ© %sPseudo-directive .file est valide seulement lors de la gÃ©nÃ©ration ELFPseudo-directive .loc est valide seulement lors de la gÃ©nÃ©ration ELFl'extension 64 bits QUICKRoT n'est pas applicable Ã cette instructionl'extension QUICKRoT requiert 4 registresPrÃ©dicat qualifiant attenduLe registre RA est sauvegardÃ© deux fois.l'opÃ©rande RC/SAE doit suivre les opÃ©randes immÃ©diatsl'opÃ©rande RC/SAE doit prÃ©cÃ©der les opÃ©randes immÃ©diatsRDRD, (RI,#offs5)RD,RSRI, #imm4Options RISC-V: -fpic gÃ©nÃ©rer du code indÃ©pendant de la position -fno-pic ne pas gÃ©nÃ©rer du code indÃ©pendant de la position (dÃ©faut) -march=ISA dÃ©finir l'architecture RISC-V -mabi=ABI dÃ©finir l'ABI RISC-V Radical Â«Â %sÂ Â» non supportÃ© ou invalideRd et Rm devraient Ãªtre diffÃ©rents dans mlaRd et Rm devraient Ãªtre diffÃ©rents dans mulRedÃ©finition de entrynum pour sysproc %sRedÃ©finition leafproc %sOption de configuration de Registre RÃ©duit (GRP16)OpÃ©rateurs de suffixe Â«Â #Â Â» redondantRegistre invalide pour H8/300Le registre at (r1) peut parfois Ãªtre corrompu par les optimisations de l'assembleur. Utilisez .set noat pour dÃ©sactiver ces optimisations (et cet avertissement).Le registre doit Ãªtre R0--R7Le registre doit Ãªtre RnLe registre doit Ãªtre un registre d'adresseLe registre doit Ãªtre ivtp ou tvtpNom de registre %s est en conflit avec un symbole du mÃªme nomNom de registre attenduNumÃ©ro de registre (R%ld) doit Ãªtre paire pour un accÃ¨s en mot double.Le numÃ©ro de registre doit Ãªtre PAIRNumÃ©ro de registre hors de la gamme 0..%uSymbole du registre %s est dÃ©jÃ dÃ©fini.Annotation de valeur de registre ignorÃ©eLe registre ne peut pas Ãªtre utilisÃ© comme prÃ©fixe d'une expression indexÃ©e [%s]Le registre ne peut pas Ãªtre utilisÃ© dans une expression absolue [%s]Le registre ne peut pas Ãªtre utilisÃ© dans une expression immÃ©diate [%s]La relaxe ne devrait jamais se produireRelaxations vers des branchements longs ne sont pas implÃ©mentÃ©s pour .arch common_v10_v32RÃ©adressage %d n'est pas supportÃ© dans le format du fichier objetValeurs relocalisables requiÃ¨rent au moins un MOT de stockageRÃ©adressage %d n'est pas supportÃ© par le format du fichier objet.RÃ©adressage %s n'est pas sÃ»r pour %sLe rÃ©adressage ne tient pas dans l'espace (valeur de rÃ©adressage = 0x%lx).Rapporter toutes anomalies Ã %s Mot rÃ©servÃ© Â«Â %sÂ Â» utilisÃ© comme paramÃ¨tre dans la macro Â«Â %sÂ Â»Rn ne peut pas recouvrir d'autres opÃ©randesL'index du registre rotatif doit Ãªtre une constante non nÃ©gativeregistre de coprocesseur S+core attenduregistre S+core attenduRegistre spÃ©cial S+core attenduOptions SH: --little gÃ©nÃ©rer du code pour un systÃ¨me Ã octets de poids faible --big gÃ©nÃ©rer du code pour un systÃ¨me Ã octets de poids fort --relax altÃ©rer les instructions jump pour de long dÃ©placements --renesas dÃ©sactiver l'optimisation des symboles de section pour la compatibilitÃ© avec l'assembleur Renesas --small aligner les sections sur des frontiÃ¨res de 4 octets, pas 16 --dsp activer sh-dsp insns et dÃ©sactiver les virgules flottantes ISA. --allow-reg-prefix autoriser Â«Â $Â Â» comme prÃ©fixe du nom de registre. --isa=[any utiliser l'isa la plus appropriÃ©e | dsp identique Ã Â«Â -dspÂ Â» | fpSHF_ALLOC n'est pas dÃ©fini pour la section GNU_MBIND: %scode SHmedia n'est pas permis dans la mÃªme section que les constantes et le code SHcompactregistre scalaire SIMD ou flottant attenduSMC n'est pas permis sur cette architectureSP et PC pas permis dans la directive .unwind_movspSP pas permis dans la liste des registresOptions SPARC: Options SPU: --apuasm Ã©muler le comportement de apuasm le registre de base SRS doit Ãªtre r13instruction SSE Â«Â %sÂ Â» est utilisÃ©eSVC pas permis sur cette architectureRegistre de prÃ©dicat SVE attenduregistre vectoriel SVE attenduTABLE DE SYMBOLE non implÃ©mentÃ©eS^# doit Ãªtre uniquement accessible en lecture seuleS^# a besoin d'une expressionMÃªme registre src/dest est utilisÃ© (Â«Â r%dÂ Â»), le rÃ©sultat est indÃ©finiMÃªme registre src/dest est utilisÃ© (Â«Â r%dÂ Â»), le rÃ©sultat est indÃ©finiMode d'adressage indexÃ©-Ã©chelle combinÃ© avec un index-Ã©chelleLe second opÃ©rande de .save contredit le .prologueLe second opÃ©rande de .%s n'est pas une constanteLe second opÃ©rande de .prologue doit Ãªtre un registre gÃ©nÃ©ralLe second opÃ©rande de .prologue doit Ãªtre le premier des %d registres gÃ©nÃ©rauxLe second opÃ©rande de .restore doit Ãªtre une constante >= 0Le second opÃ©rande de .save n'est pas un registre valideLe second opÃ©rande de .save.b doit Ãªtre un registre gÃ©nÃ©ralLe second opÃ©rande de .save.b doit Ãªtre le premier des %d registres gÃ©nÃ©rauxLe second opÃ©rande de .save.g doit Ãªtre un registre gÃ©nÃ©ralLe second opÃ©rande de .save.g doit Ãªtre le premier des %d registres gÃ©nÃ©rauxLe second opÃ©rande de .save.gf doit Ãªtre une constante non nÃ©gative de 20 bitsLe second opÃ©rande de .unwabi doit Ãªtre une constanteCommutation de section dans le code n'est pas supportÃ©.Erreur de sÃ©mantique. Ce type d'opÃ©rande ne peut Ãªtre relocalisÃ©, il doit Ãªtre une constante rÃ©solue au moment de l'assemblageValeur de dÃ©calage > 32. Utilise Branchements courts, non dÃ©finis, SVC, LDM/STMDÃ©bordement de littÃ©ral Â«Â shortÂ Â» (%ld.), mode immÃ©diat assumÃ©.Valeur immÃ©diate signÃ©e %ld est trop grandeLa taille du cadre dÃ©passe le maximum de 96 registresLa taille des registres de rotation dÃ©passe la taille du cadreQuelque chose a oubliÃ© de faire le mÃ©nage Les registres source et destination ne devraient pas Ãªtre Ã©gauxLes registres sources doivent Ãªtre dans la mÃªme unitÃ©Fausse Â«Â ,Â Â» ou mode erronÃ© d'adressage indirect par registre.OpÃ©randes parasites; (%d opÃ©randes/instructions au maximum)Â«Â #Â Â» seul est illÃ©galExtension de chaÃ®neSymboles de substitution doivent commencer par une lettreSous-type %d n'est pas reconnu.Sunplus-v2-0-0-20060510 Support pour l'arithmÃ©tique Ã 64 bits n'est pas compilÃ©.Valeurs des ARCH supportÃ©es sont:Ã‰change l'ordre des instructionsSymbole %s utilisÃ© comme opÃ©rande immÃ©diat en mode PIC.Symbole Â«Â %sÂ Â» n'a pu Ãªtre crÃ©Ã©.Symbole Â«Â %sÂ» ne peut Ãªtre Ã la fois Â«Â weakÂ Â» et Â«Â commonÂ Â»Symbole attenduSymbole manquant Symbole manquant pour .set/.equSymbole utilisÃ© comme immÃ©diat pour une instruction mbarSymbole utilisÃ© comme immÃ©diat pour une instruction de dÃ©calageSymbole utilisÃ© comme valeur immÃ©diate pour les instructions msrset/msrclrErreur de syntaxe dans le mode indexÃ©-Ã©chelle, utilisez [Rn:m] oÃ¹ n=[0..7] m={b,w,d,q}rÃ©adressage TLS par une constanterÃ©adressage TLS pas permis dans un paquet FLIXla taille de rÃ©adressage TLS ne concorde pas avec la taille de l'opÃ©randeles rÃ©adressages TLS_*_S9 ne sont pas encore supportÃ©sOptions TMS320C6000: la taille de la section TOC excÃ¨de 64kTRACE DE JETON non implÃ©mentÃ©eL'Ã©tiquette doit venir avant le prÃ©dicat qualifiant.Nom d'Ã©tiquette attenduLes Ã©tiquettes sur les pseudo-op unwind ne sont pas encore supportÃ©esLe processeur cible ne supporte pas cette instructionLe pseudo-op Â«Â %sÂ Â» n'est pas implÃ©mentÃ© L'opÃ©rande %s ne correspond pasLe pseudo-op .BTEQU n'est pas implÃ©mentÃ©.Le pseudo-op .DEFINE n'est pas implÃ©mentÃ©Le pseudo-op .ENTER n'est pas supportÃ©Le pseudo-op .LEAVE n'est pas supportÃ©Le pseudo-op .MACRO n'est pas implÃ©mentÃ©Le format de fichier 64 bits est utilisÃ© sans les instructions esame.La directive Â«Â .abi %sÂ Â» n'est pas valide pour cet architectureLa directive Â«Â .mode %sÂ Â» n'est pas valide pour cet architectureLe dÃ©bogueur va corrompre bt (r25). Si vous n'avez pas besoin de dÃ©boguer ce code, utilisez .set nobreak pour dÃ©sactiver cet avertissement.Le dÃ©bogueur va corrompre sstatus/ba (r30). Si vous n'avez pas besoin de dÃ©boguer ce code, utilisez .set nobreak pour dÃ©sactiver cet avertissement.Les options assembleur spÃ©cifiques Ã ARC ci-dessous sont dÃ©prÃ©ciÃ©es et sont acceptÃ©es uniquement pour compatibilitÃ©: L'option Â«Â --no-allow-flixÂ Â» interdit le flix multi-slot.L'identificateur de trappe doit Ãªtre une constante.Cette architecture ne supporte pas les instructions atomiquesCette architecture ne supporte pas le mmuCet assembleur ne supporte pas la gÃ©nÃ©ration %ld du processeurCet assembleur a Ã©tÃ© configurÃ© pour la cible Â«Â %sÂ Â» et le type de processeur par dÃ©faut Â«Â %sÂ Â». Cet assembleur a Ã©tÃ© configurÃ© pour la cible Â«Â %sÂ Â». L'accÃ¨s Ã ce registre de coprocesseur est dÃ©prÃ©ciÃ© avec ARMv8Cette valeur immÃ©diate requiert un alignement 0 MOD 16Cette valeur immÃ©diat requiert un alignement 0 MOD 2Cette valeur immÃ©diate requiert un alignement 0 MOD 4Cette valeur immÃ©diate requiert un alignement 0 MOD 8Cette instruction peut Ãªtre imprÃ©visible si elle est exÃ©cutÃ©e sur un cÅ“ur M-profile avec les interruptions activÃ©es.Voici la position de l'usage conflictuelCet opÃ©rande doit Ãªtre une constante au moment de l'assemblageCet opÃ©rateur produit uniquement des valeurs sur deux octets.Ce logiciel est libre; vous pouvez le redistribuer selon les termes de la version 3 de la licence GNU General Public License ou suivante. Ce programme n'est couvert par AUCUNE garantie. Thumb ne supporte pas NOP avec des indicesThumb ne supporte pas l'exÃ©cution conditionnelleThumb ne supporte pas l'indexation nÃ©gative du registreThumb ne supporte pas l'indexation du registre avec rÃ©Ã©critureThumb ne supporte pas la post-indexation du registreThumb ne supporte pas la forme de cette instruction avec 2 argumentsThumb ne supporte pas ce mode d'adressageencodage Thumb ne supporte pas un immÃ©diat icil'encodage Thumb ne supporte pas les rotationsLoad/store multiples de Thumb ne supportent pas {reglist}Thumb supporte uniquement LSL dans l'indexation dÃ©calÃ©e du registreMUL sur Thumb-2 ne doit pas activer de fanionInstruction Thumb 2 seulement valide dans la syntaxe unifiÃ©ebranchement Thumb2 hors limiteTrop peu d'opÃ©randes pour Â«Â %sÂ Â».Trop d'arguments. Â«Â %sÂ Â»Trop d'instructions pour le paquet.Trop d'opÃ©randesTrop d'opÃ©randes passÃ©s Ã l'instructionTrop d'opÃ©randes passÃ©s en revueTrop d'opÃ©randes: %sTrop de registres dÃ©pilÃ©sIdentificateur de la trappe Â«Â %ldÂ Â» est hors limite.Identificateur de la trappe doit Ãªtre entre [0x30..0x39] ou [0x40..0xff].Traite Â«Â %-*sÂ Â» comme un symbole.EssayÃ© la directive .set pour le mode non reconnu Â«Â %sÂ Â»On a essayÃ© de convertir le branchement relatif au PC en saut absoluTentative de Â«Â balÂ Â» vers %sDeux instruction IU ne peuvent pas Ãªtre exÃ©cutÃ©es en parallÃ¨leDeux instructions MU ne peuvent pas Ãªtre exÃ©cutÃ©es en parallÃ¨le.Deux instructions dans le mÃªme paquet Ã©crivent dans le registre %s ce qui n'est pas permis.incapable d'allouer de la mÃ©moire pour de nouvelles instructions Incapable de dÃ©terminer le processeur cible par dÃ©faut Ã partir de la chaÃ®ne: %sImpossible de trouver le rÃ©adressage %s pour l'instruction %sIncapable de gÃ©nÃ©rer du code conforme Â«Â %sÂ Â» sans mthc1Incapable de mÃ©langer les instructions tel que spÃ©cifiÃ©Impossible d'analyser la base TLS: %sIncapable de traiter le rÃ©adressage pour les opcodes thumb: %lxIncapable de produire un rÃ©adressage vers le symboles Â«Â %sÂ Â»Impossible d'utiliser le rÃ©adressage @pcl pour l'insn %sImpossible d'utiliser le rÃ©adressage @plt pour l'insn %sOpÃ©rande non alignÃ©. Il doit Ãªtre alignÃ© sur 16 bitsOpÃ©rande non alignÃ©. Il doit Ãªtre alignÃ© sur 32 bitsL'opÃ©rateur unaire %c est ignorÃ© en raison d'opÃ©randes erronÃ©s qui le suiveParenthÃ¨ses non pairÃ©es dans l'opÃ©rande %s.ParenthÃ¨ses non pairÃ©es dans l'opÃ©rande %dArgument .EXPORT/.IMPORT non dÃ©fini (ignorÃ©): %sConstante absolue indÃ©finie: Â«Â %sÂ Â».Registre indÃ©fini: Â«Â %sÂ Â».Espace indÃ©fini: Â«Â %sÂ Â» NumÃ©ro d'espace assumÃ© = 0.Symbole de substitution indÃ©fini Â«Â %sÂ Â»Conversion inattendu de branchement avec Â«Â %xÂ Â»CaractÃ¨re Â«Â %cÂ Â» inattendu aprÃ¨s l'opÃ©rande %d de %s.RÃ©fÃ©rence inattendue Ã un symbole dans une section qui n'est pas du codeValeur retournÃ©e inattendue [%d] Ã partir de parse_toc_entry ! DÃ©pendance non traitÃ©e %s pour %s (%s), noter %dType de rÃ©adressage non traitÃ©Registre Â«Â %sÂ Â» spÃ©cifiÃ© n'est pas implÃ©mentÃ©OpÃ©rande .syntax inconnuIdentificateur de CPU inconnu Â«Â %sÂ Â»Instruction TMS320C30 inconnue: %sCpu inconnu -mcpu=%sException inconnue: Â«Â %sÂ Â»Exception inconnueMode d'adressage indirect inconnuInstruction inconnue Â«Â %sÂ Â»Opcode Â«Â %.*sÂ Â» inconnu.Opcode inconnu Â«Â %sÂ Â»Opcode Â«Â %sÂ Â» inconnu.Opcode inconnu: Â«Â %sÂ Â»OpÃ©rateur inconnuRegistre processeur (32 bits) inconnu: Â«Â %dÂ Â»Registre processeur inconnu: Â«Â %dÂ Â»Option psr inconnue Â«Â %sÂ Â»Paire de registres inconnue - mode d'indexation relatif: Â«Â %dÂ Â»Paire de registres inconnue: Â«Â %dÂ Â»Registre inconnu: Â«Â %dÂ Â».RÃ©adressage inconnu dans md_apply_fix: %sRÃ©adressage inconnu rencontrÃ© dans md_apply_fix.OpÃ©rande de rÃ©adressage inconnu: !%sOpÃ©rande de rÃ©adressage inconnu: @%sType de segment inconnuTaille inconnue des registres en virgule flottantePseudo registre temporaire inconnuType inconnuType %c inconnu Type d'adresse littÃ©rale inconnue ou non supportÃ©eRÃ©adressage haut sans correspondantRÃ©adressage high/shigh non pairÃ©Nom d'errata de CPU non reconnu commenÃ§ant ici: %sOption non reconnue: -hiddenArgument .LEVEL non reconnu Directive .option non reconnue: %s Argument .type non reconnuCode de condition non reconnu Â«Â %sÂ Â»SpÃ©cificateur de dÃ©pendance non reconnu %d Type de champ non reconnu Â«Â %cÂ Â»Forme de correctif non reconnue (0x%08lx)Format d'adresse indirecte Â«Â %sÂ Â» non reconnuInstruction Â«Â %sÂ Â» non reconnueFormat de opcode non reconnu: Â«Â %sÂ Â»Opcode non reconnu, %s.Opcode non reconnu: Â«Â %sÂ Â»Liste d'opÃ©randes Â«Â %sÂ Â» non reconnue pour l'instruction Â«Â %sÂ Â»OpÃ©rande/registre non reconnu, %s.Option non reconnue Â«Â -x%sÂ Â»Option non reconnue aprÃ¨s -KConstante dÃ©cimale non reconnue ou non supportÃ©eInstruction parallÃ¨le Â«Â %sÂ Â» non reconnueInstruction parallÃ¨le non reconnue Â«Â %sÂ Â»Combinaison non reconnue d'instructions parallÃ¨les Â«Â %s || %sÂ Â»Type de relation de prÃ©dicat non reconnuSection non reconnue Â«Â %sÂ Â»Bit d'Ã©tat Â«Â %sÂ Â» non reconnuÃ‰tiquette struct/union non reconnue Â«Â %sÂ Â»Fonction de substitution de symbole non reconnueVersion non reconnue Â«Â %sÂ Â»Valeur immÃ©diate non signÃ©e %ld est trop grandeNombre de rÃ©adressages RISC-V %d non supportÃ©Diffusion non supportÃ©Â : Â«Â %sÂ Â»Taille du correctif %d non supportÃ©eExtension du jeu d'instruction non supportÃ©e: %sOpÃ©ration non supportÃ©e sur le rÃ©adressageGÃ©nÃ©ration %d du processeur n'est pas supportÃ©eTaille de rÃ©adressage %d non supportÃ©eUtilisation non supportÃ© de %sUtilisation non supportÃ© de .gpwordUtilisation non supportÃ©e de spChaÃ®ne non terminÃ©e aprÃ¨s l'expression absoluedirective unwind n'est pas suivie d'une instruction.Usage: %s [option...] [fichier-assembleur...] Utilisation de .def/.ref est dÃ©prÃ©ciÃ©e. Utilisez .global Ã la placeL'utilisation de PC ici est IMPRÃ‰VISIBLEL'utilisation de PC ici est dÃ©prÃ©ciÃ©eUtilisation d'une instruction de chaÃ®ne RX dÃ©tectÃ©e dans un fichier assemblÃ© sans le support des instructions chaÃ®nesUtilisation de p0 n'est pas valide dans ce contexteL'utilisation de r%u en tant que registre source est dÃ©prÃ©ciÃ©e quand r%u est le registre destinationUtiliser la directive .mmregs pour des noms de registres mappant la mÃ©moire tel que Â«Â %sÂ Â»Utilisation de $at sans ".set noat"Les instruction FPU utilisÃ©es requiÃ¨rent l'activation de l'extension FPUA utilisÃ© plus que les 48 registres rotatifs disponiblesA utilisÃ© plus que les 96 registres rotatifs disponiblesA utilisÃ© plus que les %d registres rotatifs dÃ©clarÃ©sUtilise ENTRY plutÃ´t que CODE dans la directive d'exportation pour %sL'utilisation d'une constante comme second opÃ©rande de .prologue est dÃ©prÃ©ciÃ©eUsage de l'ancien style %%hi(expr), veuillez utiliser le style PPC expr@h.Usage de l'ancien style %%lo(expr), veuillez utiliser le style PPC expr@l.Utilisation du registre temporaire (r1)Utilisation du registre temporaire (r1)Options VAX: -d LONGUEUR ignorÃ© -J ignorÃ© -S ignorÃ© -t FICHIER ignorÃ© -T ignorÃ© -V ignorÃ© les registres VFP doivent Ãªtre adjacentsregistre VFP en simple ou double prÃ©cision attenduregistre VFP en simple prÃ©cision attenduregistre VFP en simple, double ou Neon en quadruple prÃ©cision attenduregistre systÃ¨me VFP attenduregistre VFP/Neon en double prÃ©cision attenduErreur VIP_BEGIN:%sVLIW violation de la contrainte d'empaquetageVLIW empaquetage utilisÃ© pour -mno-packOptions VMS: -+ encoder (sans tronquer) les noms plus longs que 64 caractÃ¨res -H afficher les nouveaux symboles aprÃ¨s une troncation du hachage -replace/-noreplace activer ou non l'optimisation des appels de procÃ©dure Options VMS: -+ hash encoder les noms plus longs que 31 caractÃ¨res -1 traiter les Â«Â constÂ Â» en mode compatible avec gcc 1.x -H afficher les nouveaux symboles aprÃ¨s le rabotage hash -h NUM ne pas hacher les noms avec des casses mÃ©langÃ©es et ajuster la casse: 0 = majuscule, 2 = minuscule, 3 = prÃ©server la casse -v"VERSION" inscrire le numÃ©ro de VERSION du code assemblÃ© Valeur %d n'entre pas dans un champ de %d bits signÃ©Valeur %d n'entre pas dans un champ de %d bits non signÃ©Valeur %ld pas alignÃ©e par 2 pour un branchement relatif au PC sur 10 bits.Valeur %ld pas alignÃ©e par 2 pour un branchement relatif au PC sur 9 bits.Valeur %ld trop grande pour un branchement de 10 bits relatif au PCValeur %ld trop grande pour un branchement de 8 bits relatif au PCValeur %ld trop grande pour un branchement de 9 bits relatif au PCValeur de ENTRY_FR doit Ãªtre dans la plage 12..21 Valeur de ENTRY_GR doit Ãªtre dans la plage 3..18 Valeur de ENTRY_SR doit Ãªtre 3 La valeur du paramÃ¨tre Â«Â %sÂ Â» de la macro Â«Â %sÂ Â» a dÃ©jÃ Ã©tÃ© spÃ©cifiÃ©eValeur n'est pas dans les bornes de 16 bits: %ldValeur n'est pas dans les bornes signÃ©es de 16 bits: %ldValeur n'est pas dans les bornes non signÃ©es de 4 bits: %ldValeur n'est pas dans les bornes non signÃ©es de 5 bits: %ldValeur n'est pas dans les bornes de 6 bits: %ldValeur n'est pas dans les bornes non signÃ©es de 6 bits: %ldValeur n'est pas dans les bornes de 8 bits: %ldValeur n'est pas dans les bornes signÃ©es de 8 bits: %ldValeur hors des limites 16 bits.Valeur hors des limites 3 bits.Valeur hors des limites 4 bits.Valeur hors des limites 5 bits.Valeur tronquÃ©e Ã 62 bitsLa variable est atteinte via une ancre en lecture seule de petites donnÃ©es, mais elle n'est pas dans une section en lecture seule de petites donnÃ©esLa variable est atteinte via une ancre en lecture/Ã©criture de petites donnÃ©es, mais elle n'est pas dans une section en lecture/Ã©criture de petites donnÃ©esOption appliquÃ©e Ã une instruction trÃ¨s courte, cÃ d vous ne pouvez le faire sur une chaÃ®ne NULLMÃ©moire virtuelle Ã©puisÃ©eAvertissement: Attention: condition hors d'un bloc IT pour Thumb.Attention: registre en double (r%d) dans la liste des registresAttention: erreur interne: on a oubliÃ© de fixer endndx de %sAttention: gamme de registres n'est pas en ordre croissantÃ‰critures dans le registre Â«Â %sÂ Â» pas permises.DÃ©placement erronÃ© %dNombre d'opÃ©randes d'entrÃ©e erronÃ©Nombre erronÃ© d'opÃ©randesNombre d'opÃ©randes de sortie erronÃ©Nombre erronÃ© d'opÃ©randes dans le dÃ©faut, vÃ©rifiez ns32k-opcodes.hMauvais registre dans la liste des registres en virgule flottanteMauvais registre en mode registre indirect.Taille erronÃ©e du registre de pointeur pour l'architectureregistre accumulateur XScale invalidel'option Xtensa des littÃ©raux absolus n'est pas supportÃ©e; ignorÃ©e[-mwarn-syms]: L'affectation fait correspondre un symbole Ã une instruction ARM: %sÃ©tiquettes [0-9]H ne peuvent Ãªtre mÃ©langÃ©es avec des dot-pseudosÃ©tiquettes [0-9]H ne peuvent apparaÃ®tre seuls sur une ligneindexation du [PC] est bannie[]index identique Ã ()+registre: imprÃ©visible[]index identique Ã -()registre: imprÃ©visible[no-]generics est dÃ©prÃ©ciÃ©; utilisez plutÃ´t [no-]transform[no-]relax est dÃ©prÃ©ciÃ©; utilisez plutÃ´t [no-]transformsymbole [tocv] n'est pas un symbole tocÂ«Â %s %dÂ Â» aprÃ¨s Â«Â %s %dÂ Â» dans %s:%uÂ«Â %s %dÂ Â» mais pas encore de fragment ouvertÂ«Â %s%sÂ Â» ne peut Ãªtre utilisÃ© comme masque d'Ã©critureÂ«Â %s%sÂ» n'est pas permis avec Â«Â %s%cÂ Â»Â«Â %sÂ Â» Combinaison de registres de comptage illÃ©gale.Â«Â %sÂ Â» Utilisation de registre illÃ©gale.Â«Â %sÂ Â» Utilisation illÃ©gale des registres.les dÃ©finitions de Â«Â %sÂ Â» et Â«Â %sÂ Â» ne peuvent pas Ãªtre supprimÃ©es dans Â«Â %sÂ Â» â€“ Â«Â %sÂ Â»Â«Â %sÂ Â» ne peut Ãªtre rendu Ã©quivalent au symbole commun Â«Â %sÂ Â»ne peut supprimer la dÃ©finition de Â«Â %sÂ Â» dans Â«Â %sÂ Â» â€“ Â«Â %sÂ Â» {section %s}ne peut supprimer la dÃ©finition de Â«Â %sÂ Â» dans Â«Â %sÂ Â» {section %s} â€“ Â«Â %sÂ Â»Â«Â %sÂ Â» ne peut Ãªtre liÃ©e par version au symbole commun Â«Â %sÂ Â»Â«Â %sÂ Â» ne peut pas aller dans %s du modÃ¨le %sÂ«Â %sÂ Â» ne peu pas Ãªtre transformÃ© en prÃ©dicatÂ«Â %sÂ Â» ne peut pas Ãªtre utilisÃ© iciÂ«Â %sÂ Â» ne peut pas Ãªtre utilisÃ© avec Â«Â %sÂ Â»Â«Â %sÂ Â» n'entre pas dans le modÃ¨le %sÂ«Â %sÂ Â» n'entre pas dans le paquetÂ«Â %sÂ Â» ne supporte pas le NaN historiqueÂ«Â %sÂ Â» a un rÃ©sultat indÃ©finiÂ«Â %sÂ Â» est dÃ©jÃ l'alias de %s Â«Â %sÂ Â»Â«Â %sÂ Â» est dÃ©prÃ©ciÃ©, utilisez Â«Â %sÂ Â»Â«Â %sÂ Â» n'est pas une expression %s valideÂ«Â %sÂ Â» n'est pas un qualificateur de paramÃ¨tre valable pour Â«Â %sÂ Â» dans la macro Â«Â %sÂ Â»Â«Â %sÂ Â» n'est pas supportÃ© en mode 64 bitsÂ«Â %sÂ Â» n'est pas supportÃ© sur Â«Â %s%sÂ Â»Â«Â %sÂ Â» n'est pas supportÃ© sur Â«Â %sÂ Â»Â«Â %sÂ Â» n'est pas valable ici (attendu Â«Â %c%s%s%cÂ Â»)Â«Â %sÂ Â» est uniquement supportÃ© en mode 64 bitsÂ«Â %sÂ Â» doit Ãªtre le dernier dans le paquetÂ«Â %sÂ Â» doit Ãªtre le dernier dans le groupe d'instructionsÂ«Â %sÂ Â» opÃ©rande %d doit utiliser le segment Â«Â %sesÂ Â»Â«Â %sÂ Â» devrait Ãªtre un opÃ©rande de ce .endpÂ«Â %sÂ Â» symbole sans fonction qui la prÃ©cÃ¨deÂ«Â %sÂ Â» a dÃ©jÃ Ã©tÃ© dÃ©finiÂ«Â %sÂ Â» a dÃ©jÃ Ã©tÃ© utilisÃ© comme nom de paramÃ¨tre (ou tout autre locale)Â«Â %sÂ Â» n'a pas Ã©tÃ© dÃ©fini Ã l'intÃ©rieur d'une procÃ©dureÂ«Â %sÂ Â» n'a pas Ã©tÃ© spÃ©cifiÃ© avec le .proc prÃ©cÃ©dentopÃ©rateur de numÃ©ro de sÃ©rie Â«Â &Â Â» n'est pas supportÃ©Â«Â )Â Â» requisÂ«Â ,Â Â» requisÂ«Â .abi 32Â Â» mais les options de la ligne de commande ne spÃ©cifient pas un ABI 32 bitsÂ«Â .abi 64Â Â» mais les options de la ligne de commande ne spÃ©cifient pas un ABI 64 bitsÂ«Â afÂ Â» doit apparaÃ®tre seulÂ«Â fp=32Â Â» utilisÃ© avec une ABI de 64 bitsÂ«Â fp=32Â Â» utilisÃ© avec un processeur MIPS R6Â«Â fp=64Â Â» utilisÃ© avec une ABI de 32 bitsÂ«Â fp=64Â Â» utilisÃ© avec un fpu de 32 bitsÂ«Â fp=xxÂ Â» ne peut Ãªtre utilisÃ© avec Â«Â singlefloatÂ Â»Â«Â fp=xxÂ Â» utilisÃ© avec un processeur sans les instructions ldc1/sdc1Â«Â gp=32Â Â» utilisÃ© avec une ABI de 64 bitsÂ«Â gp=64Â Â» utilisÃ© avec une ABI de 32 bitsÂ«Â gp=64Â Â» utilisÃ© avec un processeur de 32 bitsÂ«Â nooddspregÂ Â» ne peut pas Ãªtre utilisÃ© avec une ABI de 64 bitsÂ«Â noreorderÂ Â» doit Ãªtre initialisÃ© avant Â«Â nomacroÂ Â»un NOP pourrait Ãªtre nÃ©cessaire avant le EINTun NOP pourrait Ãªtre nÃ©cessaire ici Ã cause de changements successifs dans l'Ã©tat d'interruptionun grand nombre avec soulignÃ©s ne peut avoir plus de 8 chiffres hexadÃ©cimaux dans n'importe quel motun grand nombre avec soulignÃ©s doit avoir exactement 4 motsun registre de destination doit Ãªtre fournisun %s diffÃ©rent a dÃ©jÃ Ã©tÃ© spÃ©cifiÃ©, est maintenant %sun registre n'a pas d'adresseun rÃ©adressage de cet opÃ©rande implique un dÃ©bordementsections absolues ne sont pas supportÃ©esl'accumulateur n'est pas une destination valableaddende utilisÃ© sans $DSBT_INDEXle calcul d'adresse a besoin d'un symbole proche fortement dÃ©finioffset de l'adresse doit Ãªtre alignÃ© sur un demi motoffset de l'adresse doit Ãªtre alignÃ© sur un motl'adresse interdit #l'adresse interdit ()l'adresse interdit ()+l'adresse interdit -()l'adresse interdit @l'adresse interdit []adresse interdit un spÃ©cificateur de longueur de dÃ©placementadresse interdit l'utilisation de registreadresse trop grande pour la table de vecteur jmp/jsrles unitÃ©s d'adresse doivent Ãªtre parmi %smode d'adressage non supportÃ©alias = %s valeur d'alignement non reconnue, utilisation de la taillealignment n'est pas un nombre positifalignment n'est pas une puissance de 2l'alignement doit Ãªtre une constantealignement nÃ©gatif, 0 utilisÃ©alignement nÃ©gatif; 0 assumÃ©alignment n'est pas une puissance de 2le remplissage pour alignement (%lu octet) n'est pas un multiple de %ldle remplissage pour alignement (%lu octets) n'est pas un multiple de %ldalignement trop grand, %d utilisÃ©alignement trop grand: %u assumÃ©alignement trop grand; %d assumÃ©alignment trop grand; %d assumÃ©alignment trop grand; %ld assumÃ©alignements plus grand que %d octets ne sont pas supportÃ©s dans les sections .textinstruction dÃ©jÃ assemblÃ©ecombinaison de fanions ambiguÃ« - directive Â«Â .profilerÂ Â» ignorÃ©e.taille d'opÃ©rande mÃ©moire ambigu pour Â«Â %sÂ Â»taille d'opÃ©rande ambiguÃ« pour Â«Â %sÂ Â»un .indirect_symbol doit Ãªtre dans un pointeur de symbole ou une section Ã©bauchÃ©e.l'extension d'architecture Â«Â %sÂ Â» n'est pas permise pour l'architecture de base actuelleles extensions d'architecture doivent Ãªtre spÃ©cifiÃ©es dans l'ordre alphabÃ©tiquearchitecture Â«Â %sÂ Â» n'est pas reconnuearchitecture bousculÃ© de Â«Â %sÂ Â» Ã Â«Â %sÂ Â» sur Â«Â %sÂ Â»fonctionalitÃ©s d'architecture Ã la fois activÃ©es et dÃ©sactivÃ©esconflits de opcode d'architecture avec ceux d'instruction(s) dÃ©jÃ dÃ©finie(s)variante d'architecture invalideassembler en code Thumbassembler pour un systÃ¨me Ã octets de poids fortassembler pour un systÃ¨me Ã octets de poids faibleassembleur 0x%08x, attendu %sl'Ã©tat d'assemblage n'est pas mis pour le premier fragment de la section %ssuppose %s sur le symboleassume que tous les membres du groupe Â«Â %sÂ Â» sont COMDATau plus %d opÃ©randes de dÃ©placement sont permisau plus %d opÃ©randes immÃ©diats sont permisattachement de l'en-tÃªte de copyright %s: %sattachement de l'en-tÃªte de version %s: %stentative d'utiliser .org/.space vers l'arriÃ¨re ? (%ld)tentative de marche arriÃ¨re avec .space/.bes ? (%ld)tentative d'ajouter un indirect_symbol Ã une Ã©bauche ou une section de rÃ©fÃ©rence avec un Ã©lÃ©ment de taille nulle Ã %stentative d'allouer des donnÃ©es dans une section absoluetentative d'allouer des donnÃ©es dans une section communetentative de branchement dans un segment diffÃ©renttentative de remplir une section absolue avec une valeur non nulletentative de remplir la section Â«Â %sÂ Â» avec une valeur non nulletentative pour obtenir la valeur du symbole non rÃ©solu Â«Â %sÂ Â»tentative de dÃ©placement de .org vers l'arriÃ¨retentative de redÃ©finir le symbole Â«Â %sÂ Â»tentative de recrÃ©er une entrÃ©e unwindtentative de redÃ©finir Â«Â %sÂ Â» avec une longueur diffÃ©rentetentative de redÃ©finition du pseudo-op Â«Â %sÂ Â» ignorÃ©etentative de redÃ©finition de symboletentative de redÃ©finition de l'alias typÃ©tentative de stocker un nombre dÃ©cimal dans une section absoluetentative de stocker un nombre dÃ©cimal dans la section Â«Â %sÂ Â»tentative de stocker une chaÃ®ne non vide dans la section Â«Â %sÂ Â»tentative de stocker une valeur non nulle dans la section Â«Â %sÂ Â»tentative de stockage d'une valeur dans une section absoluetentative d'utiliser une instruction ARM sur un processeur ne supportant que Thumb -- Â«Â %sÂ Â»rÃ©fÃ©rence arriÃ¨re vers une Ã©tiquette inconnue Â«Â %d:Â Â»segment .common erronÃ© %sdirective .fmask erronÃ©edirective .frame erronÃ©eformat .longcall erronÃ©directive .mask erronÃ©edirective .mask/.fmask erronÃ©edirective .nan erronÃ©eformat .relax erronÃ©segment .reserve erronÃ© -- segment BSS attendudirective .section erronÃ©e: nÃ©cessite a,e,v,w,x,M,S,G,T dans la chaÃ®neDirective .section erronÃ©e: nÃ©cessite a,l,w,x,M,S,G,T dans la chaÃ®nedirective .section erronÃ©e: nÃ©cessite a,o,s,w,x,M,S,G,T dans la chaÃ®nemauvaise directive .section: nÃ©cessite a,s,w,x,M,S,G,T dans la chaÃ®nedirective .section erronÃ©e: nÃ©cessite a,v,w,x,M,S dans la chaÃ®neDirective .section erronÃ©e: nÃ©cessite a,w,x,M,S,G,T dans la chaÃ®neformat .uses erronÃ©directive .weakext erronÃ©einformation de dÃ©bug COFF erronÃ©emauvais spÃ©cificateur de champ RVC Â«Â C%cÂ Â» mauvais alignementmauvais alignement de %d octets dans le bassin des littÃ©rauxmauvais argument pour la directive %s_check.mauvais argument pour la directive de syntaxe.arguments erronÃ©s pour l'instructionregistre de base erronÃ©: doit Ãªtre r0mauvais bitmask spÃ©cifiÃ© aprÃ¨s APSRappel erronÃ© de MD_ATOF()appel erronÃ© Ã md_atofmauvais opÃ©randes de sortie pmuls combinÃ©sidentificateur de co-processeur erronÃ©defsym erronÃ©; format est --defsym nom=valeurmauvais type d'Ã©lÃ©ment pour l'instructionmauvais caractÃ¨re d'Ã©chappement dans la chaÃ®neexpression erronÃ©esyntaxe de l'expression erronÃ©elittÃ©ral de virgule flottante erronÃ©: %sconstante en virgule flottante erronÃ©e: dÃ©bordement de l'exposantconstante erronÃ©e en virgule flottante; code d'erreur inconnu=%dmauvais format pour ifc ou ifncformat erronÃ© de OPT NEST=profondeurmauvaise fragmentation Ã %p: correction %ld adresse %ld %ld mauvaise unitÃ© fonctionnelle pour l'opÃ©rande %u de Â«Â %.*sÂ Â»valeur immÃ©diate erronÃ©e pour un offset 8 bits (%ld)valeur immÃ©diate erronÃ©e pour l'offset (%ld)instruction Â«Â %sÂ Â» erronÃ©emauvais format d'instructionsyntaxe de l'instruction erronÃ©emauvaise longueur de listemauvaise longueur de liste pour une recherche dans la tablemauvais type de liste pour l'instructionmauvaise taille littÃ©rale opÃ©rande mÃ©moire erronÃ© Â«Â %sÂ Â»mauvais nombre d'opÃ©randes Ã Â«Â %.*sÂ Â»mauvais offset 0x%08lX (doit Ãªtre un nombre 8-bits de mots)mauvais offset 0x%08lX (doit Ãªtre alignÃ© sur un mot)mauvais offset 0x%08lX (seulement 12 bits disponibles pour grandeur)mauvais offset 0x%08lX (seulement 8 bits disponibles pour la grandeur)opcode ou opÃ©randes erronÃ©smauvais opÃ©rande %u de Â«Â %.*sÂ Â»mauvaise combinaison d'opÃ©randes pour Â«Â %.*sÂ Â»expression absolue erronÃ©e ou irrÃ©ductibleexpression absolue erronÃ©e ou irrÃ©ductible; zÃ©ro assumÃ©numÃ©ro de co-processeur erronÃ© ou manquanttype de rÃ©adressage mauvais ou non traitÃ©: 0x%02xmauvais numÃ©ro de routine de personnalitÃ©mauvais prÃ©dicat Â«Â %sÂ Â»mauvaise limite dans la liste des registresmauvaise expression de registremauvais registre pour mrsmauvais registre pour l'opÃ©rande %u de Â«Â %.*sÂ Â»mauvais registre pour un post-indexmauvais registre dans []liste de registres erronÃ©eliste de registres erronÃ©e: %smauvais nom de registre Â«Â %sÂ Â»mauvais nom de registre: %snumÃ©ro de registre erronÃ©: %smauvais registre ou paire de registres aprÃ¨s l'opÃ©rande %u de Â«Â %.*sÂ Â»mauvaise paire de registres pour l'opÃ©rande %u de Â«Â %.*sÂ Â»mauvaise gamme de registremauvais Ã©tat de relÃ¢cheexpression de rÃ©adressage erronÃ©emauvaise expression de rÃ©adressage pour Â«Â %sÂ Â»type erronÃ© de correctif de rÃ©adressage (%d)segment erronÃ©mauvaise taille %d dans le spÃ©cifieur de typemauvaise taille %d dans le spÃ©cificateur de largeur de vecteurregistre de dÃ©part erronÃ©: r0 et r15 invalidesmauvaise constante en tant que chaÃ®ne de caractÃ¨resmauvais suffixe de symbolemauvais type pour le registremauvais type pour un scalairemauvais type dans une instruction Neonvaleur invalide (%s) pour %smauvais type d'arrangement vectorielspÃ©cificateur psr erronÃ©/manquantdirective .dim mal composÃ©edirective .dim mal composÃ©e est ignorÃ©edirective .size mal composÃ©edirective .dim mal composÃ©e est ignorÃ©eExpression mal composÃ©e prÃ¨s de %sbase et offset doivent provenir de la mÃªme unitÃ©registre de base attenduregistre de base spÃ©cifiÃ© mais est zÃ©roregistre de base rÃ©Ã©crit et recouvre un des registres de transfertregistre de base rÃ©Ã©crit et recouvre le second registre de transfertunitÃ© de base doit Ãªtre soit A0 ou A1l'unitÃ© de base doit Ãªtre une parmi %scible-bfd = %s bfd_set_section_flags: %ssystÃ¨me Ã octets de poids fort n'est pas supportÃ©grand nombre invalidegrand nombre invalide; zÃ©ro assumÃ©grand nombre tronquÃ© Ã %d octetgrand nombre tronquÃ© Ã %d octetsle champ de bits s'Ã©tend au delÃ de la fin du registreblx vers Â«Â %sÂ Â» dans la fonction d'Ã©tat ARM ISA changÃ© en blblx vers fonction Thumb Â«Â %sÂ Â» depuis l'Ã©tat Thumb ISA changÃ© en blles deux insns pour !gpdisp!%ld doivent Ãªtre dans la mÃªme sectionenregistrement br_gr avant l'enregistrement de rÃ©gion !enregistrement br_mem avant l'enregistrement de rÃ©gion !bra ou bsr avec symbole non dÃ©fini.branchement %s est toujours vraidÃ©bordement de la gamme de saut d'adresses (0x%lx)le branchement doit Ãªtre la derniÃ¨re instruction du bloc IToffset de branchement %d hors limiteoffset de branchement %d hors des limites %d Ã %doffset de branchement hors limite opÃ©rande de branchement a un dÃ©calage impair (%lx) branchement hors limiteprÃ©diction de branchement invalide pour cet opcodeÃ©chec de la relÃ¢che du branchement la relaxation de branchement n'est pas supportÃ©e dans Â«Â %sÂ Â»la frÃ©quence de branchement cible doit Ãªtre plus grande que 0cible du branchement pas alignÃ©e sur un motbranchement vers un symbole dans un autre mode ISAsaut vers une adresse mal alignÃ©e (0x%lx)brancher ou sauter vers la fin d'une boucle peut dÃ©clencher un errata matÃ©rielÂ«Â breakÂ Â» en dehors de la boucle structurÃ©eune diffusion est nÃ©cessaire pour un opÃ©rande de ce typediffusion pas sur un opÃ©rande de mÃ©moire sourceassemblage cassÃ©, aucune tentative d'assemblagela constante de dÃ©compte d'octet %ld est hors des limites [1..%d]dÃ©placement d'octet hors limiteoctet ou demi-mot non valide pour un registre de baseappel Ã l'adresse cible 0x%08x hors des limites 0x%08x Ã 0x%08xappel de md_convert_frag appel de md_convert_frag appel de md_estimate_size_before_relax appel de md_estimate_size_before_relax appel de tc_aout_fix_to_chars ne peut faire un rÃ©adressage relatif au PC de %d octetsne peut relocaliser %d octetsne peut rÃ©soudre l'expressionseuls deux registres consÃ©cutifs peuvent Ãªtre chargÃ©sseuls deux registres consÃ©cutifs peuvent Ãªtre stockÃ©sseuls deux registres consÃ©cutifs peuvent Ãªtre transfÃ©rÃ©sne peut indexer[] un registre, parce qu'il n'a pas d'adressel'index de l'opÃ©rande ne peut pas Ãªtre changÃ©ne peut fermer %s: %sne peut fermer Â«Â %sÂ Â»ne peut crÃ©er %s: %sne peut crÃ©er le groupe: %sne peut crÃ©er le rÃ©adressagene peut crÃ©er la section %sne peut encoder le registre Â«Â %s%sÂ Â» dans l'instruction nÃ©cessitant le prÃ©fixe REX.ne peut Ã©tendre la fragmentationne peut Ã©tendre la fragmentation de %lu caractÃ¨rene peut Ã©tendre la fragmentation de %lu caractÃ¨resimpossible de remplir %ld octet dans la section %s de %s: Â«Â %sÂ Â»impossible de remplir %ld octets dans la section %s de %s: Â«Â %sÂ Â»ne peut repÃ©rer le correctif pointÃ© par .usesne peut repÃ©rer l'opcodene peut repÃ©rer l'opcode ne peut repÃ©rer l'opcode prÃ©cÃ©dentne peut traiter l'expressionne sait pas encore traiter la gÃ©nÃ©ration de littÃ©raux/Ã©tiquettesne peut traiter un segment non absolu dans Â«Â %sÂ Â»ne peut traiter un TYPE OP indÃ©finine peut hacher %s: %sne peut avoir de rÃ©adressage pour ipushne peut rendre global le symbol de registre Â«Â %sÂ Â»ne peut mÃ©langer des arguments positionnels et des mots clÃ©sne peut mÃ©langer un modificateur de rÃ©adressage avec un dÃ©calage explicitene peut ouvrir %s en lecture: %sne peut ouvrir %s: %sne peut ouvrir Â«Â %sÂ Â» en Ã©criturene peut ouvrir un bfd sur stdout %sne peut ouvrir le fichier de librairie de macro Â«Â %sÂ Â» pour lecture: %sne peut faire une prÃ©-dÃ©crÃ©mentationne peut lire Ã partir de %s: %sl'indexe d'un alias scalaire ne peut pas Ãªtre redÃ©finile type d'un alias de registre ne peut pas Ãªtre redÃ©finile type ne peut pas Ãªtre redÃ©fini pour un opÃ©randene peut reprÃ©senter le type de rÃ©adressage %sne peut rÃ©soudre Â«Â %sÂ Â» {section %s} - Â«Â %sÂ Â» {section %s}ne peut rÃ©soudre la valeur du symbole Â«Â %sÂ Â»ne peut initialiser les fanions de section pour la section %sne peut dÃ©buter l'Ã©criture de la section .mdebug: %sne peut utiliser un format COBR avec une Ã©tiquette externeun quadruple registre Neon ne peut pas Ãªtre utilisÃ© icine peut utiliser R0 iciun alignement ne peut pas Ãªtre utilisÃ© avec cette instructionne peut utiliser la partie haute du registre dans l'opÃ©rande %dne peut utiliser le registre Â«Â %s%sÂ Â» comme opÃ©rande %d dans Â«Â %sÂ Â».impossible d'Ã©crire %ld octet dans la section %s de %s: Â«Â %sÂ Â»impossible d'Ã©crire %ld octets dans la section %s de %s: Â«Â %sÂ Â»ne peut assembler l'instruction DSP, l'option DSP n'est pas activeÂ : %sne peut assembler l'instruction FPU, l'option FPU n'est pas activeÂ : %sne peut assembler dans un fragment littÃ©ralne peut prÃ©-dÃ©crÃ©menter et post-incrÃ©menter en mÃªme tempsne peut brancher vers une adresse impairene peut changer .bundle_align_mode Ã l'intÃ©rieur de .bundle_lockne peut changer la section ou la sous-section Ã l'intÃ©rieur de .bundle_lockindex ne peut pas Ãªtre combinÃ© avec optionne peut combiner prÃ© et post indexationne peut convertir le symbole d'expression %s en rÃ©adressage complexene peut produire un rÃ©adressage 64 bitsimpossible de crÃ©er le nombre Ã virgule flottantene peut dÃ©coder le format de l'instructionne peut dÃ©finir le symbole Â«Â %sÂ Â» dans la section absolueimpossible de dÃ©terminer la taille de l'instruction Thumb. Utilisez plutÃ´t .inst.n/.inst.wne peut faire un rÃ©adressage %s %u octetsne peut faire un rÃ©adressage relatif au PC de %u octetsne peut faire un rÃ©adressage sur %u octetsne peut produire le rÃ©adressage %s relatif au PC%s%sne peut produire un rÃ©adressage %s sur le symbole subsy %simpossible d'encoder un terme mal alignÃ© dans un champ rÃ©adressable (0x%lx)l'opcode Â«Â %sÂ Â» ne peut Ãªtre encodÃ©ne peut encoder l'opcode Â«Â %sÂ Â» dans le format Â«Â %sÂ Â» demandÃ©impossible de trouver un trampoline convenablene peut gÃ©nÃ©rer un type de rÃ©adressage pour le symbole %s, code %sne peut honorer le suffixe de largeur -- Â«Â %sÂ Â»impossible de faire un saut relatif vers une position absolueune instruction qui n'utilise pas d'unitÃ© fonctionnelle ne peut pas Ãªtre masquÃ©ene peut outrepasser le type de section zerofill pour Â«Â %s,%sÂ Â»ne peut empaqueter %s et %s ensemblesne peut empaqueter %s et %s ensembles avec une instruction 16 bitsne peut empaqueter %s dans le slot P1ne peut empaqueter %s avec une instruction 16 bitsne peut reprÃ©senter le rÃ©adressage %s dans le fichier objetne peut reprÃ©senter le rÃ©adressage %s dans ce format de fichier objetne peut reprÃ©senter le rÃ©adressage %s dans ce format1 de fichier objetne peut reprÃ©senter le rÃ©adressage Â«Â %sÂ Â» dans le fichier objetne peut reprÃ©senter le type de rÃ©adressage %sne peut reprÃ©senter le type de rÃ©adressage %s en mode x32ne peut rÃ©soudre le paramÃ¨tre @slotcountne peut fixer literal_prefix Ã l'intÃ©rieur d'un fragment littÃ©ralne peut utiliser Â«Â %sÂ Â» dans cette sectionne peut utiliser l'adressage indirect avec le PCne peut utiliser le registre partiel %s pour l'adressagele post-indexage ne peut pas Ãªtre utilisÃ© avec un adressage relatif au PCle post-indexage ne peut pas Ãªtre utilisÃ© avec cette instructionne peut pas utiliser un index de registre avec un adressage relatif au PCun index de registre ne peut Ãªtre utilisÃ© avec cette instructionla rÃ©Ã©criture ne peut pas Ãªtre utilisÃ©e avec un adressage relatif au PCcette instruction ne peut pas utiliser la rÃ©Ã©criturecanonique = %s constante de caractÃ¨res trop grandecaractÃ¨re suivant le nom n'est pas Â«Â #Â Â»cmpu ne supporte pas le code de condition %soffset du coprocesseur hors limiteregistre de coprocesseur attenducode est conforme ATPCSle code utilise un compteur de programme de 26 bitsle code utilise un compteur de programme de 32 bitsvirgule attendue entre les opÃ©randesvirgule attenduevirgule manquante dans .xstabsalignement du commun n'est pas une puissance de 2la comparaison doit Ãªtre faite avec un registre ou #0valeur du code de condition %s (%d) trop grandecode de condition invalide pour jrregistre du code de condition devrait Ãªtre 0 ou 4 pour %s, Ã©tait %dregistre du code de condition devrait Ãªtre pair pour %s, Ã©tait %dcondition n'est pas suivie par insn conditionnablecondition requisela condition sa ne peut Ãªtre utilisÃ©e icile branchement conditionnel ou l'opÃ©rande de l'instruction jal rÃ©fÃ©rence R%ld de l'instruction arithmÃ©tique ou logique prÃ©cÃ©dente.branchement conditionnel hors limitecible du branchement conditionnel pas alignÃ©e sur un motles infixes conditionnels sont dÃ©prÃ©ciÃ©s dans la syntaxe unifiÃ©el'instruction conditionnelle ne peut utiliser le fanion Bl'instruction conditionnelle ne peut utiliser le fanion Gl'instruction conditionnelle ne peut utiliser le fanion Rattributs d'extension ISA conflictuels.expressions confuses de rÃ©adressageconfusion dans les paramÃ¨tres formelsla constante ne tient pas dans 4 bitsexpression constante attendueexpression constante ou liste de registres attendueexpression constante attendueexpression constante attendue.gÃ©nÃ©rateur constant pour le registre de destination dans %sgÃ©nÃ©rateur constant pour le registre source dans %sdÃ©calage constant requitconstante hors limite pour les bornes de 8 bits: %dlongueur de dÃ©calage constante requiseconstant trop grande pour Ãªtre insÃ©rÃ©e dans l'instructionvaleur constante requiseregistre de contrÃ´le Â«Â %sÂ Â» pas supportÃ© sur cette architectureregistre de contrÃ´le attendu, mais a eu '%.6s'convert_frag les longueurs des instructions core et copro doivent Ãªtre au total 32 bits.les longueurs des instructions core et copro doivent Ãªtre au total 64 bits.valeur de registre coeur %s (%d) trop granden'a pu assembler: %sn'a pu construire la transition de %s => %sn'a pu analyser INSN_PATTERN Â«Â %sÂ Â»n'a pu analyser INSN_REPL Â«Â %sÂ Â»n'a pu analyser la dÃ©finition du modÃ¨lene peut initialiser l'architecture et la machinene peut escamoter jusqu'Ã %ld dans le fichier Â«Â %sÂ Â»ne peut mettre Ã jour l'architecture et la machinen'a pas pu Ã©crire la section .mdebug: %sn'a pu trouver un format d'instruction validen'a pu trouver le rÃ©adressage Ã utilisercpu Â«Â %sÂ Â» n'est pas reconnutype de CPU = %s cpu4: pas de conversion de PUSH #4 vers une forme plus courtecpu4: pas de conversion de PUSH #8 vers une forme plus courtecr%ld est un registre de contrÃ´le rÃ©servÃ©ctoff() n'est pas supportÃ© par l'ABI rh850. Utilisez plutÃ´t -mgcc-abirÃ©adressage ctoff() utilisÃ© sur une instruction qui ne le supporte pasl'opcode de l'instruction custom %u est hors des limites %u Ã %uregistres d0/d1emplacement dangereux pour MULS/MULU; utilisez un alignement plus grandÂ«Â __gcc_isr %dÂ Â» ballantÂ«Â __gcc_isrÂ Â» ballantdÃ©pendance des donnÃ©es: %s %s -- %s %s (%d/%d bulles)donnÃ©es dans une section exÃ©cutableÃ©lÃ©ment de donnÃ©e avec un alignement plus grand que la positionle registre de transfert de donnÃ©es ne peut pas Ãªtre un demi-motle masque par dÃ©faut n'est pas permisdest et source1 doivent Ãªtre le mÃªme registredest dois recouvrir un registre sourcedestinationla destination pour une addition/soustraction peut seulement Ãªtre R2 ou R3la destination d'une multiplication peut seulement Ãªtre R0 ou R1opÃ©rande de destination doit Ãªtre un registre de 16 bitsopÃ©rande de destination doit Ãªtre une adresse absolue de 16 bitsopÃ©rande de destination doit Ãªtre un registre de 8 bitsregistre de destination est le mÃªme pour les insns parallÃ¨lesregistre de destination modifiÃ© par adresse dÃ©placement-aprÃ¨s-modificationle registre de destination doit Ãªtre un mot entierregistre de destination doit Ãªtre r1le registre de destination est le mÃªme que la base de rÃ©Ã©criture arriÃ¨reregistre de destination devrait avoir un numÃ©ro pairunitÃ© de destination doit Ãªtre RDutilisation d'un registre global dÃ©tectÃ©e n'est pas couvert pas un pseudo-op .registerdiffÃ©rence de deux symboles uniquement supportÃ©e avec .long, .short ou .bytedirective %s ne peut pas Ãªtre inversÃ©edirective .big rencontrÃ©e alors que l'option -big est requisedirective .little rencontrÃ©e alors que l'option -little est requisedirective LOC depuis l'intÃ©rieur de la paire BSPEC/ESPEC n'est pas supportÃ©edirective LOCAL doit Ãªtre placÃ© dans le code ou le datadirective invalide Ã l'intÃ©rieur de paquetsdÃ©sactiver les avertissements Ã propos de symboles qui correspondent Ã des instructionsdiscrimateur plus petit que zÃ©rodÃ©placement trop grandle dÃ©placement doit Ãªtre un nombre non signÃ© de 8 bitsdÃ©placement provoque un dÃ©bordement du champ de 12 bitsdÃ©placement provoque un dÃ©bordement du champ de 8 bitsdÃ©placement pour dÃ©finir le symbole %s provoque un dÃ©bordement du champ de 12 bitsdÃ©placement pour dÃ©finir le symbole %s provoque un dÃ©bordement du champ de 8 bitsdÃ©placement pour symbole indÃ©fini %s provoque un dÃ©bordement du champ de 12 bitsdÃ©placement pour symbole indÃ©fini %s provoque un dÃ©bordement du champ de 8 bits dÃ©placement trop grand (%d)dÃ©placement trop grand pour cette architecture; a besoin de 68020 ou plusdiv / mul sont des instructions rÃ©servÃ©esdivision par zÃ©rodivision par zÃ©rodivision par zÃ©ro lors de l'initialisation de Â«Â %sÂ Â»dla utilisÃ© pour charger un registre 32 bits; il est recommandÃ© d'utiliser lane pas afficher de messages d'erreur verbeuxne pas avertir en cas d'utilisation d'une fonctionnalitÃ© dÃ©prÃ©ciÃ©en'est pas pairÃ© avec le dÃ©but %s%s Ã %s:%dn'utilisez pas la syntaxe Rn-Rm avec un pas non unitairel'abandon du registre %d dans la section %s ne correspond pas Ã l'utilisation du registre %dabandon du registre %d dans la section %s prÃ©cÃ©demment utilisÃ© dans la section %sla valeur de dÃ©calage dsp immÃ©diate n'est pas une constante!tlsgd!%ld en double!tlsldm!%ld en doubleÂ«Â .elseÂ Â» en doubledirective .fnstart en doubledirective .handlerdata en doubledirective .personality en doubledirective .personalityindex en doubleignore l'opÃ©rateur d'Ã©tiquette de donnÃ©es dupliquÃ©instruction %s en doublemacro %s en doubleÂ«Â %sÂ Â» en doublespÃ©cificateur de bit psr en doubleles Ã©lÃ©ments doivent Ãªtre plus petits que la rÃ©gion inversÃ©eÂ«Â elseÂ Â» sans Â«Â ifÂ Â» correspondantemit_one_bundle: opÃ©rande dynamique inattenduÃ©tiquette de champ vide pour ISnom de symbole vide dans .def; ignorÃ©liste de registres vectoriels videÃ©mulations non traitÃ©s dans cette configurationfin du fichier aprÃ¨s la prÃ©sence d'un seul caractÃ¨re apostrophe; \0 insÃ©rÃ©fin du fichier dans le commentairefin de fichier dans le commentaire; nouvelle ligne insÃ©rÃ©efin de fichier dans le caractÃ¨re d'Ã©chappementfin de fichier dans un commentaire multilignesfin du fichier dans la chaÃ®ne; Â«Â %cÂ Â» insÃ©rÃ©fin de fichier Ã l'intÃ©rieur d'un conditionnelfin du fichier n'est pas Ã la fin de la ligne; nouvelle ligne insÃ©rÃ©efin de macro Ã l'intÃ©rieur d'un conditionnelfin de la liste des registres vectoriels pas trouvÃ©eerreur de fin de ligneÂ«Â endfÂ Â» sans Â«Â forÂ Â»Â«Â endiÂ Â» sans Â«Â ifÂ Â» correspondantdernier registre doit Ãªtre r15Â«Â endwÂ Â» sans Â«Â whileÂ Â»taille d'entitÃ© pour SHF_MERGE non spÃ©cifiÃ©einstruction d'entrÃ©e avec dÃ©crÃ©mentation de pile < 16erreur lors de la vÃ©rification du dÃ©bordement â€“ assembleur endommagÃ©erreur de construction %s table pseudo-op: %serreur lors de l'analyse de la liste Ã©lÃ©ment/structureerreur lors de l'initialisation des fanions de Â«Â %sÂ Â»: %serreur lors de l'initialisation des fanions pour Â«Â .sbssÂ Â»: %serreur: directive #foo() non supportÃ©e utilisÃ©e sur un symboletaille estimÃ©e estimate_size_before_relax a Ã©tÃ© appelÃ©numÃ©ro paire de registre requisnumÃ©ro pair de registre requisopÃ©randes en excÃ¨s vers %sexcÃ¨s d'opÃ©randes: Â«Â %sÂ Â»#constante attendu#n attendu comme premier argument de %s%c attenduÂ«Â ,Â Â» attendue aprÃ¨s le nom de sectionÂ«Â ,Â Â» attendue aprÃ¨s le nom de symboleÂ«Â ,Â Â» attendue aprÃ¨s la taille du symboleÂ«Â ]Â Â» attendu au lieu de %c dans Â«Â %sÂ Â», attendu.L, .W ou .B attendu pour le registre dans le mode d'adressage indexÃ©0 opÃ©rande attendu pour l'Ã©tiquette gÃ©nÃ©rÃ©e0 ou 1 attenduopÃ©rande ou ou attendu attendu, attendu, attendu<Ã©tiquette> , attendu@(exp, reg16) attenduregistre EP attenduÂ«%sÂ» aurait dÃ©jÃ dÃ» Ãªtre fixÃ© pour .vtable_inheritun nom %s est attendu suivi par une Â«Â ,Â Â»expression d'adresse attenduealignement attendu aprÃ¨s la tailleparenthÃ¨ses fermante attenduevirgule attenduevirgule attendue aprÃ¨s Â«Â %sÂ Â»virgule attendue aprÃ¨s le nom de l'instructionvirgule attendue aprÃ¨s l'opcode majeurvirgule attendue aprÃ¨s le nomvirgule attendue aprÃ¨s le nom Â«Â %sÂ Â»virgule attendue aprÃ¨s le nom Â«Â %sÂ Â» dans la directive .localentryvirgule attendue aprÃ¨s le nom Â«Â %sÂ Â» dans la directive .sizevirgule attendue aprÃ¨s le nom dans .symvervirgule attendue aprÃ¨s le nom dans .vtable_entryvirgule attendue aprÃ¨s le nom dans .vtable_inheritvirgule attendue aprÃ¨s le mode de registrevirgule attendue aprÃ¨s un numÃ©ro de registrevirgule attendue aprÃ¨s le nom de symbolevirgule attendue aprÃ¨s le nom de symbole: reste de la ligne ignorÃ©.virgule ou deux points attendus aprÃ¨s le nom de symbole: reste de la ligne ignorÃ©virgule attendue comme sÃ©parateurexpression constante attendue comme premier argument de %sexpression constante attendue, %s obtenuconstante dans la plage 2..16 attendueconstante ou nom de registre attendu comme argument de insn RPTvaleur constante attendue comme argument de RPTexpression attendueexpression attendue, %s obtenule patron de remplissage attendu est manquantle premier argument de %s Ã©tait attendu dans la plage 1-4index attenduconstante numÃ©rique attendueun opÃ©rande attendu pour le littÃ©ral gÃ©nÃ©rÃ©chaÃ®ne entre apostrophes attendueregistre attenduregistre attendu comme second argument de %sliste de registre attenduenom de registre ou constante attendu comme premier argument de %snombre simple attendusymbole attendunom de symbole attendumode d'adressage valide attendu pour mova: "@(disp, ea.sz),ERn"la valeur du premier argument de %s aurait du tenir dans 20 bits} attendu%c attendu prÃ¨s de %s) attendu] attenduÂ«Â )Â Â» attendu aprÃ¨s le facteur d'Ã©chelle dans Â«Â %sÂ Â»Â«Â ,Â Â» ou Â«Â )Â Â» attendu aprÃ¨s le registre de base dans Â«Â %sÂ Â»Â«Â ,Â Â» ou Â«Â )Â Â» attendu aprÃ¨s le registre d'index dans Â«Â %sÂ Â»registre attendu pour l'opÃ©rande %dopÃ©randes dÃ©limitÃ©s par des virgules sont attendusopÃ©randes de registres dÃ©limitÃ©s par des virgules sont attendusregistre de contrÃ´le attenduON ou OFF attendu aprÃ¨s .listregistre d'index ou facteur d'Ã©chelle attendu aprÃ¨s Â«Â ,Â Â»; a obtenu Â«Â %cÂ Â»instruction de branchement indirect attendue aprÃ¨s Â«Â notrackÂ Â»registre indirect Â«Â ($rA)Â Â» attenduregistre indirect Â«Â ($rX)Â Â» attenduinstruction verrouillable attendue aprÃ¨s l'instruction Â«Â lockÂ Â»mnÃ©monique attendue; rien de trouvÃ©chaÃ®ne d'opcode attendu en mode auto testopÃ©rande attendu aprÃ¨s Â«Â ,Â Â»; rien de trouvÃ©opÃ©rande attendu avant Â«Â ,Â Â»; rien de trouvÃ©prÃ©fixe attendu; rien de trouvÃ©registre attendufacteur d'Ã©chelle attendu de 1, 2, 4, ou 8: a obtenu Â«Â %sÂ Â»instruction de branchement valide attendue aprÃ¨s Â«Â bndÂ Â»{ attenduexpression n'entre pas dans un OCTETexpression n'entre pas dans un MOTerreur dans l'expressionl'expression doit Ãªtre une constantel'expression n'est pas une constanteexpression hors limite: utilise 0 par dÃ©fautexpression hors limite: utilise 1 par dÃ©fauterreur de syntaxe dans l'expressionexpression trop complexeinstruction Ã©tendue dans la plage de dÃ©lai de branchementinstruction Ã©tendue dans la plage de dÃ©laiopÃ©rande Ã©tendu demandÃ© mais non requiseil n'est pas permis d'Ã©tendre le dÃ©calageextension Â«Â %sÂ Â» n'est pas reconnuel'extension ne s'applique pas Ã l'architecture de basearguments superflus pour .LABEL sont ignorÃ©s.caractÃ¨res superflus Â«Â %sÂ Â» Ã la fin de l'expression constante Â«Â %sÂ Â»caractÃ¨res superflus Â«Â %sÂ Â» Ã la fin de l'expression immÃ©diate Â«Â %sÂ Â»caractÃ¨res superflus Â«Â %sÂ Â» Ã la fin de l'opÃ©rande Â«Â %sÂ Â»caractÃ¨res superflus Â«Â %sÂ Â» Ã la fin de l'opÃ©rande absolu Â«Â %sÂ Â»accolade fermante superfluedeux-points supplÃ©mentairevirgule supplÃ©mentairepoint supplÃ©mentaireaccolade ouvrante superflueles trucs supplÃ©mentaires sur la ligne sont ignorÃ©scaractÃ¨res superflus Ã la fin du type de section numÃ©riqueshift superflu dans l'opÃ©rande de l'instruction de shifta Ã©chouÃ© pour %d Ã©chec de la vÃ©rification de l'Ã©tat de santÃ© du registre gÃ©nÃ©ral.Ã©chec de la vÃ©rification de l'Ã©tat de santÃ© du regnum.la vÃ©rification de l'Ã©tat de santÃ© a Ã©chouÃ©la vÃ©rification de l'Ã©tat de santÃ© a Ã©chouÃ©.la vÃ©rification de l'Ã©tat de santÃ© a Ã©chouÃ©: long_jumpla vÃ©rification de l'Ã©tat de santÃ© a Ã©chouÃ©: short_jumpla vÃ©rification de l'Ã©tat de santÃ© du cas spÃ©cial insn a Ã©chouÃ© Ã©chec Ã l'assemblage de l'instructionÂ : Â«Â %sÂ Â»Ã©chec lors de l'analyse des fanionsÃ©chec de lecture de la table d'instructions %s erreur lors de l'initialisation des fanions de Â«Â %sÂ Â»: %sÃ©chec de l'initialisation des sous-sections par symbolesÃ©chec d'initialisation des informations de dÃ©bug: %s.file factice aprÃ¨s un vrai fichierla frÃ©quence de transfert implicite (fall through frequency) doit Ãªtre plus grande que 0champ fx_size trop petit pour contenir %dtaille du champ doit Ãªtre 16 quand la valeur est relocalisablevaleur du champ Â«Â %sÂ Â» trop complexe pour un champ de bitsvaleur du champ tronquÃ©elargeur du champ Â«Â %sÂ Â» trop complexe pour un champs de bitslargeur du champ %lu trop grande pour s'insÃ©rer dans %d octet: tronquÃ© Ã %d bitslargeur du champ %lu trop grande pour s'insÃ©rer dans %d octets: tronquÃ© Ã %d bitscinquiÃ¨mele fichier s'est terminÃ© avec un bloc IT ouvert.fichier non trouvÃ©: %snumÃ©ro de fichier %ld est dÃ©jÃ allouÃ©le numÃ©ro du fichier est plus petit que unnom de fichier passe outre une frontiÃ¨re de pagemotif de remplissage trop long, tronquÃ© Ã %upremierle premier et second opÃ©randes seront les mÃªmes registresle premier opÃ©rande est un nombre en virgule flottantele premier opÃ©rande est trop grand pour un entier signÃ© de 16 bitsle premier opÃ©rande est trop grand pour un dÃ©placement de 24 bitspremier registre doit Ãªtre r4le premier registre de transfert doit Ãªtre paircorrectifs n'ont pas tous Ã©tÃ© dÃ©placÃ©s Ã partir de %sfanion pour instruction {c}psr attenduregistre de virgule flottante devrait Ãªtre pair, Ã©tait %darguments en virgule flottante sont dans les registres FPconstante en virgule flottante trop grandenombre flottant invalidenombre flottant invalide; zÃ©ro assumÃ©nombres flottants pas implÃ©mentÃ©sexpression en virgule flottante attendueformat = %s noms de format uniquement valable dans des paquetsrepÃ©rÃ© %d opÃ©rande pour Â«Â %sÂ Â»: %d attendusrepÃ©rÃ© %d opÃ©randes pour Â«Â %sÂ Â»: %d attendusÂ«Â %cÂ Â» trouvÃ©, attendait: Â«Â %cÂ Â»quatriÃ¨meenregistrement fr_mem avant l'enregistrement de rÃ©gion !fr_var %lu < longueur %dfr_var (%ld) < longueur (%d)valeur de bits de fraction hors limiteregistre de trame attendu, utilise $%dtaille de trame spÃ©cifiÃ©e deux foisenregistrement frgr_mem avant l'enregistrement de rÃ©gion !unitÃ© fonctionnelle dÃ©jÃ masquÃ©el'unitÃ© fonctionelle est dÃ©jÃ masquÃ©e pour l'opÃ©rande %u de Â«Â %.*sÂ Â»unitÃ© fonctionnelle dÃ©jÃ utilisÃ©e dans ce paquet d'exÃ©cutionle rebut aprÃ¨s la spÃ©cification d'index est ignorÃ©rebut Ã la fin de la ligneinstruction suivie de rebutsgÃ©nÃ©rer du code PICget_expanded_loop_offset: opcode invalideenregistrement gr_gr avant l'enregistrement de rÃ©gion !enregistrement gr_mem avant l'enregistrement de rÃ©gion !nom de groupe pour SHF_GROUP non spÃ©cifiÃ©La section de groupe Â«Â %sÂ Â» n'a pas de signature de groupehandlerdata dans un cadre cantunwindnombres flottants matÃ©riel entrent en conflit avec le fpu spÃ©cifiÃ©division matÃ©riellele rÃ©sultat est IMPRÃ‰VISIBLE si le registre de base est dans la liste des registres pendant une rÃ©Ã©criturevoici le Â«Â elseÂ Â» du conditionnel non terminÃ©voici le Â«Â .elseÂ Â» prÃ©cÃ©dentvoici le Â«Â .ifÂ Â» prÃ©cÃ©dentvoici le dÃ©but du conditionnel non terminÃ©rÃ©adressage hi() utilisÃ© sur une instruction qui ne le supporte pasrÃ©adressage hi0() utilisÃ© sur une instruction qui ne le supporte pasbits supÃ©rieurs initialisÃ©s dans l'expression de la liste des registreshint ne peut pas Ãªtre utilisÃ© dans une unitÃ© Bhint dans une unitÃ© B pourrait Ãªtre traitÃ© comme un nophint.b pourrait Ãªtre traitÃ© comme un nophint.b ne devrait pas Ãªtre utilisÃ©registre de contrÃ´le iWMMXt attenduregistre de donnÃ©e ou de contrÃ´le iWMMXt attenduregistre de donnÃ©e iWMMXt attenduregistre scalaire iWMMXt attenduia64.md_begin: ne peut adresser par hachage Â«Â %sÂ Â»: %sidentificateur+constante@%s signifie identificateur@%s+constanteidentificateur+constante@got signifie identificateur@got+constantesi le registre de rÃ©Ã©criture est dans la liste, il doit Ãªtre le plus bas dans la listetentative ignorÃ©e de redÃ©finition du symbole Â«Â %sÂ Â».ignore la tentative de redÃ©finir le registre intÃ©grÃ© Â«Â %sÂ Â»tentative ignorÃ©e de redÃ©finition du symbole %signore la tentative de supprimer la dÃ©finition du registre intÃ©grÃ© Â«Â %sÂ Â»ignore la tentative d'utiliser .unreq sur un nom de registre fixe: Â«Â %sÂ Â»mauvais alignement ignorÃ©changement d'attributs de section ignorÃ© pour %schangement d'entitÃ© de taille de section pour %schangement de type de section ignorÃ© pour %son ignore le dÃ©limiteur Â«Â :Â Â» supplÃ©mentaire de Â«Â -rename-sectionÂ Â»ignore la valeur de remplissage dans la section absolueignore la valeur de remplissage dans la section Â«Â %sÂ Â»type de section incorrect de %s a Ã©tÃ© ignorÃ©ignore la spÃ©cification invalide de '-rename-section': Â«Â %sÂ Â»ignore la sortie de la macro en dehors d'une dÃ©finition de macro.opÃ©randes ignorÃ©es: %s ignore la redÃ©finition de l'alias du registre Â«Â %sÂ Â»ignore le type .endian non reconnu Â«Â %sÂ Â»iif conversion interne pcrel/binaryiif conversion interne pcrel/pointeurtaille de rÃ©adressage %s illÃ©gale: %ddirective .stab%c illÃ©gale, mauvais caractÃ¨reexpression .stabx illÃ©gale; zÃ©ro assumÃ©indirection double illÃ©galeexpression illÃ©galeopÃ©rande de registre immÃ©diat illÃ©gal %srÃ©fÃ©rence indirecte illÃ©galelittÃ©ral illÃ©galopcode %s illÃ©gal pour MCU %sopÃ©rande illÃ©galopÃ©rande illÃ©gal - nom de registre repÃ©rÃ© alors qu'aucun n'Ã©tait attenduopÃ©randes illÃ©gauxplage de versions matÃ©riel cibles illÃ©galeregistre illÃ©gal aprÃ¨s @registre illÃ©gal aprÃ¨s @-registre illÃ©gal inclus dans la listenumÃ©ro de registre illÃ©galutilisation illÃ©gale de la resource dans un paquetutilisation illÃ©gale du registre de contrÃ´leutilisation illÃ©gale du registre du coprocesseurimm3imm5 devrait Ãªtre >= 2immÃ©diat 0 ne peut Ãªtre utilisÃ© iciimmÃ©diat 1 ou 2 attenduune valeur immÃ©diate ne peut pas Ãªtre dÃ©placÃ©e par une seule instructionprÃ©fixe # attendu avec une expression immÃ©diatela valeur immÃ©diate Ã des bits mis en dehors de la taille de l'opÃ©randeimmÃ©diat n'est pas une puissance de deuximmÃ©diat doit Ãªtre 1 ou 2offset immÃ©diat pas alignÃ© sur 2 octetsoffset immÃ©diat pas alignÃ© sur 4 octetsoffset immÃ©diat est hors limiteopÃ©rande immÃ©diat illÃ©gal avec un saut absoluopÃ©rande immÃ©diat ne correspond pasopÃ©rande immÃ©diat est trop grandopÃ©rande immÃ©diat requisopÃ©rande immÃ©diat requiert iwMMXt2la somme des opÃ©randes immÃ©diats est plus grande que 32valeur immÃ©diate hors limitevaleur immÃ©diate hors limite pour une insertionvaleur immÃ©diate hors limite pour une opÃ©ration de rÃ©trÃ©cissementvaleur immÃ©diate hors limite pour un dÃ©calagevaleur immÃ©diatevaleur immÃ©diate %d hors des limites %d Ã %dvaleur immÃ©diate %llu hors des limites %u Ã %luvaleur immÃ©diate %u hors des limites %u Ã %uvaleur immÃ©diate 0x%x tronquÃ©e Ã 0x%xvaleur immÃ©diate hors limitela valeur immÃ©diate doit Ãªtre un multiple de %d Ã l'opÃ©rande %d â€” Â«Â %sÂ Â»valeur immÃ©diate pas permise quand la source et la destination diffÃ¨rentvaleur immÃ©diate hors limitevaleur immÃ©diate hors limite valeur immÃ©diate hors limite: limitÃ© Ã [0, 16]valeur immÃ©diate hors limite: limitÃ© Ã [1, 32]zÃ©ro immÃ©diat attendunombre incorrect d'opÃ©randes. Attendait %d, a obtenu %darguments inappropriÃ©s pour l'opcode Â«Â %sÂ Â»arguments inappropriÃ©s pour l'opcode Â«Â %sÂ Â»fanion %i incompatible dans la directive de lignetypes inconsistants dans une instruction Neonutilisations inconsistantes de .cfi_sectionscondition incorrect dans le bloc ITformat incorrect pour une instruction de multiplication parallÃ¨lenombre d'opÃ©randes incorrect dans la premiÃ¨re instructionnombre d'opÃ©randes incorrect dans la seconde instructionRegistre incorrect Â«Â %s%sÂ Â» utilisÃ© avec le suffixe Â«Â %cÂ Â»registre incorrect dans la liste des registresnumÃ©ro de registre incorrect, ignorÃ©registres index et de destination devraient Ãªtre distinctsindex pas permis dans une liste de registresoffset d'index hors limiteregistre d'index recouvre le registre de transfertregistre d'index spÃ©cifiÃ© mais est zÃ©rovaleur d'index trop grande pour %sregistre vectoriel indexÃ© attendu%s indirect sans Â«Â *Â Â»insertion de Â«Â %sÂ Â» dans la table de hachage des alias %s a Ã©chouÃ©: %sinsertion de Â«Â %sÂ Â» dans la table de hachage des noms %s a Ã©chouÃ©: %sinsertion de Â«Â %sÂ Â» dans la table de hachage des chaÃ®nes: %sinsertion de Â«Â %sÂ Â» dans la table de symboles a Ã©chouÃ©: %sinsertion de Â«Â %sÂ Â» dans la table de hachage d'Ã©tiquettes: %sinsertion d'un NOP avant EINTinsn ne peut Ãªtre combinÃ© avec un traitement parallÃ¨le insninsn ne peut Ãªtre combinÃ© avec non nopxinsn ne peut Ãªtre combinÃ© avec non nopyinsn ne peut Ãªtre combinÃ© avec pmulsl'instruction %s ne peut pas suivre une autre instruction E/S.l'instruction %s ne peut pas suivre une autre instruction qui accÃ¨de Ã la mÃ©moire.l'instruction %s requiert %d opÃ©randel'instruction %s requiert %d opÃ©randesinstruction %s requiert un mcu MSP430Xinstruction %s requiert l'activation de l'extension AUDIOinstruction %s requiert l'activation de l'extension DIV & DX_REGSinstruction %s requiert l'activation de l'extension DX_REGSinstruction %s requiert l'activation de l'extension FPUinstruction %s requiert l'activation de l'extension FPU_DPinstruction %s requiert l'activation de l'extension FPU_MACinstruction %s requiert l'activation de l'extension FPU_SPinstruction %s requiert l'activation de l'extension STRINGinstruction %s requiert l'activation de l'extension de performanceinstruction %s requiert l'activation de l'extension de performance IIl'instruction %s.a n'existe pasinstruction %s: rÃ©sultat est toujours fauxinstruction %s: rÃ©sultat est toujours vraiinstruction Â«Â %.*sÂ Â» ne peut pas Ãªtre transformÃ©e en prÃ©dicatinstruction Â«Â %sÂ Â» ne peut Ãªtre exÃ©cutÃ©e en parallÃ¨le.instruction Â«Â %sÂ Â» est valable seulement pour le M32R2instruction Â«Â %sÂ Â» est valable seulement pour le M32RXinstruction Â«Â %sÂ Â» pas permise aprÃ¨s Â«Â xacquireÂ Â»l'instruction Â«Â %sÂ Â» n'est pas supportÃ©e en mode 16 bits.l'adresse de l'instruction n'est pas un multiple de 16l'adresse de l'instruction n'est pas un multiple de 2l'adresse de l'instruction n'est pas un multiple de 4l'adresse de l'instruction n'est pas un multiple de 8l'instruction ne peut pas Ãªtre conditionnellel'instruction n'opÃ¨re pas sur des valeurs par pairesl'instruction n'accepte pas un adressage prÃ© indexÃ©l'instruction n'accepte pas un index de registre mis Ã l'Ã©chellel'instruction n'accepte pas ce mode d'adressagel'instruction n'accepte pas un adressage dÃ©sindexÃ©l'instruction n'autorise pas un index dÃ©calÃ©l'instruction n'accepte pas l'adressage dÃ©sindexÃ©l'instruction ne supporte pas la rÃ©Ã©criturel'instruction ne prend pas un type de blocforme d'instruction pas supportÃ©e par cette architecture.l'instruction accÃ¨de implicitement Ã R31 du chargement prÃ©cÃ©dent.l'instruction est toujours non-conditionnellemnÃ©monique d'instruction trop longueÂ : %sinstruction non permise dans un bloc ITinstruction pas supportÃ©e en mode Thumb16instruction requiert une Ã©tiquetteinstruction requiert une Ã©tiquette ou une valeur dans l'Ã©tendue -511:512Instruction requiert une Ã©tiquette SANS '$'l'instruction requiert un index de registrela sÃ©quence d'instruction (write a0, branchement, retw) peu dÃ©clencher un errata matÃ©rielles instructions Ã©crivent dans le mÃªme registre de destination.registre entier 32 bits attenduregistre entier 64 bits attenduOpÃ©rande entier hors limiteregistre entier ou SP attenduregistre entier ou zÃ©ro attenduregistre entier attenduregistre entier attendu dans le registre opÃ©rande Ã©tendu/dÃ©calÃ©registre entier, zÃ©ro ou SP attenduconfusion interne: rÃ©adressage dans une section sans contenuerreur interne dans l'analyse des argumentserreur interne: [%s] code inattendu [%lx] dans le symbole froberreur interne: mauvaise valeur CFA #%derreur interne: mauvais type d'argument %cerreur interne: mauvais ID de propriÃ©tÃ© de fichier %derreur interne: opcode microMIPS erronÃ© (longueur incorrecte: %u): %s %serreur interne: opcode microMIPS erronÃ© (dÃ©saccord opcode/longueur): %s %serreur interne: mauvais rÃ©adressage #%derreur interne: index de la section de base hors limiteserreur interne: descripteur de l'opcode endommagÃ© pour Â«Â %s %sÂ Â» erreur interne: ne peut exporter le type de rÃ©adressage %d (Â«Â %sÂ Â»)erreur interne: ne peut adresser par hachage Â«Â %sÂ Â»: %serreur interne: ne peut adresser par hachage Â«Â %sÂ Â»: %s erreur interne: le registre aux Â«Â %sÂ Â» ne peut Ãªtre hashÃ©: %serreur interne: la macro Â«Â %sÂ Â» ne peut Ãªtre hashÃ©: %serreur interne: l'opcode Â«Â %sÂ Â» ne peut Ãªtre hashÃ©: %serreur interne: l'opcode Â«Â %sÂ Â» ne peut Ãªtre hashÃ©: %serreur interne: ne peut installer un correctif pour le type de rÃ©adressage %d (Â«Â %sÂ Â»)erreur interne: Ã©chec de l'allocation de %d pointeurs indirectsymbolerreur interne: correctif non contenu Ã l'intÃ©rieur du fragmenterreur interne: macro invalideerreur interne: opÃ©rande lookup/get a Ã©chouÃ©erreur interne: perte de l'opcode: Â«Â %sÂ» Â«%sÂ Â» erreur interne: plus de symboles mach-o indirects qu'attenduerreur interne: rÃ©adressage %d (Â«Â %sÂ Â») n'est pas supportÃ© dans le format du fichier objeterreur interne: format DWARF2 inconnuerreur interne: Ã©tat de vÃ©rification nop inconnuerreur interne: nom d'option Â«Â %sÂ Â» inconnuerreur interne; ne peut gÃ©nÃ©rer le rÃ©adressage Â«Â %sÂ Â»erreur interne ? ne peut gÃ©nÃ©rer le rÃ©adressage Â«Â %sÂ Â»erreur interne ? ne peut gÃ©nÃ©rer le rÃ©adressage Â«Â %sÂ Â» (%d, %d)Ã©chec interne dans parse_register_listinconsistence interne dans %s: bdap.w sans symboleinconsistence interne dans %s: bdapq pas de symboleproblÃ¨me interne d'inconsistance dans %s: %lxproblÃ¨me interne d'inconsistance dans %s: instruction externe %04lxproblÃ¨me interne d'inconsistance dans %s: fr_subtype %dproblÃ¨me interne d'inconsistance dans %s: fr_symbol %lxproblÃ¨me interne d'inconsistance dans %s: instruction %04lxproblÃ¨me interne d'inconsistance dans %s: symbole rÃ©soluproblÃ¨me interne d'inconsistance: %s appelÃ© pour %d octetsrÃ©adressage interne (type: IMMÃ‰DIAT) n'est pas corrigÃ©interne: BFD_RELOC_MMIX_BASE_PLUS_OFFSET n'est pas rÃ©solu vers la sectioninterne: expression GREG non rÃ©solue vers la sectioninterne: mauvais opcode RISC-V (bits 0x%lx indÃ©finis): %s %sinterne: opcode RISC-V erronÃ© (erreur de masque): %s %sinterne: opcode RISC-V erronÃ© (type d'opÃ©rande inconnu Â«Â %cÂ Â»): %s %sinterne: opcode RISC-V erronÃ© (type d'opÃ©rande inconnu Â«Â C%cÂ Â»): %s %sinterne: mauvais opcode mips (bits 0x%08lx dÃ©finis): %s %sinterne: mauvais opcode mips (bits 0x%08lx dÃ©fini deux fois): %s %sinterne: mauvais opcode mips (bits 0x%08lx indÃ©finis): %s %sinterne: opcode mips erronÃ© (erreur de masque): %s %serreur interne: ne peut adresser par hachage Â«Â %sÂ Â»: %sinterne: mmix_prefix_name mais le prÃ©fixe est videinterne: type de relaxation inattendue %d:%dinterne: Ã©tiquette %s non traitÃ©einterne: type d'opÃ©rande inconnuÂ : %s %srÃ©adressage interne (type: OFFSET_IMM) n'est pas corrigÃ©vecteur d'interruption pour l'instruction trap est hors limiteoption %s invalide pour le processeur %soption -march= invalide: Â«Â %sÂ Â»option -mavxscalar= invalide: Â«Â %sÂ Â»option -mevexlig= invalide: Â«Â %sÂ Â»option -mevexrcig= invalide: Â«Â %sÂ Â»option -mevexwig= invalide: Â«Â %sÂ Â»option -mfence-as-lock-add= invalide: Â«Â %sÂ Â»option -mmnemonic= invalide: Â«Â %sÂ Â»option -momit-lock-prefix= invalide: Â«Â %sÂ Â»option -moperand-check= invalide: Â«Â %sÂ Â»option -mrelax-relocations= invalide: Â«Â %sÂ Â»option -msse-check= invalide: Â«Â %sÂ Â»option -msyntax= invalide: Â«Â %sÂ Â»option -mtune= invalide: Â«Â %sÂ Â» invalide dans --march=: %svaleur @slotcount invalideexpression BSPEC invalidemauvaise expression FPA immÃ©diateregistre HI invalide avec une immÃ©diatexpression LOC invalideparamÃ¨tre NaN invalide -mnan=%sopÃ©rande relatif au PC est invaliderÃ©fÃ©rence PIC invalideadresse VSIB invalideWakeOnStatus %ld invalideadresse WideBux XFR %ld invalideabi invalide -mabi=%sregistre accumulateur invalideadresse invalidemode d'adressage invalideextension d'architecture invalidearchitecture invalide %sarchitecture invalide -A%sarchitecture invalide -xarch=%sarchitecture invalide -z%soption d'architecture invalide -m%s, ignorÃ©eargument Â«Â %sÂ Â» invalide pour -fdebug-prefix-maptentative invalide de dÃ©claration d'un nom de version externe comme nom par dÃ©faut pour le symbole Â«Â %sÂ Â»argument invalide pour auto-litpool-limitargument invalide pour auto-litpool-limit (la plage est 100-10000)type de barriÃ¨re invalideregistre de base invalide pour un registre de dÃ©calageopÃ©rande de branchement invalidedÃ©calage d'octets de branchement invalidenom d'opÃ©ration de cache invalidecaractÃ¨re %s invalide au dÃ©but de l'opÃ©rande %d Â«Â %sÂ Â»caractÃ¨re %s invalide avant l'opÃ©rande %dcaractÃ¨re %s invalide dans la mnÃ©moniquecaractÃ¨re invalide %s dans l'opÃ©rande %dcaractÃ¨re invalide en entrÃ©eopÃ©rande de coprocesseur invalidecondition invalidecode de condition Â«Â %sÂ Â» invalidenom du code de condition invalideoption de configuration Â«Â %sÂ Â» invalide dans la rÃ¨gle de transition Â«Â %sÂ Â»constante invalideconstante invalide (%lx) aprÃ¨s le correctifdÃ©calage de table constant %ld invalideconstante invalide: expression %d bits n'est pas dans la gamme %d..%dconstante invalide: expression %d bits n'est pas dans la gamme %u..%uconstante invalide: %d n'est pas un entier alignÃ© sur un motconstante invalide: expression 10 bits pas dans la gamme [-2^9, 2^9-1]constante invalide: expression 20 bits pas dans la gamme -2^19..2^19-1constante invalide: expression 25 bits pas dans la gamme [-16777216, 16777215]constante invalide: expression 32 bits n'est pas dans la gamme [-0x80000000, 0x7fffffff]constante invalide: expression 32 bits n'est pas dans la gamme [0, 0xffffffff]constante invalide: expression 32 bits pas alignÃ©e sur un motconstante invalide: expression de bit non dÃ©finienom de registre de contrÃ´le invalidetaille de dÃ©placement par dÃ©faut invalide Â«Â %sÂ Â». Utilisera par dÃ©faut %d.opÃ©rande de mÃ©moire destination invalideregistre de destination invalideliste de registres destination invalideregistre de destination invalideÃ©lÃ©ment de sÃ©lecteur invalidetaille d'Ã©lÃ©ment %d invalide et combinaison %c de taille de vecteurboucle vide invalideexpression invalide dans l'Ã©valuation du type %dexpression invalide pour l'opÃ©rande %i de Â«Â %sÂ Â»expression invalide dans chargement/stockage multiplesexpression invalide dans l'opÃ©randeexpression invalide dans l'adressefanion Â«Â %sÂ Â» invalidepaire de registres en virgule flottante invalide. Les opÃ©randes valables pour une paire de registres fp sont 0, 1, 4, 5, 8, 9, 12 ou 13.constante en virgule flottante erronÃ©equatriÃ¨me registre invalidetaille de cadre invalideexpression hvc invalideidentificateur invalide pour Â«Â .ifdefÂ Â»immÃ©diat invalideposition du champ immÃ©diat invalideimmÃ©diat invalide pour le calcul d'adresse (valeur = 0x%08lX)immÃ©diat invalide pour un calcul d'adresse de piletaille immÃ©diate invalidevaleur immÃ©diate invalideimmÃ©diat invalide: %ld est hors limiteregistre d'index invalidetaille d'index invalide pour un Â«Â coldfireÂ Â»taille de registre indirect invalidemauvaise instruction Â«Â %sÂ Â» aprÃ¨s Â«Â %sÂ Â»instruction invalide pour cette architecture; a besoin de mauvaise forme d'instructiontaille d'instruction choisie invalide (%d)suffixe d'instruction invalidederniÃ¨re instruction invalide pour une boucle avec zÃ©ro-overheadle champ de longueur spÃ©cifiÃ© est invalidelongueur invalide pour la directive .scommoption de listage invalide Â«Â %cÂ Â»constante littÃ©ral invalide: le bassin doit Ãªtre plus prÃ¨slrlive Â«Â %luÂ Â» invalidemachine invalide Â«Â %sÂ Â»mode machine Â«Â %sÂ Â» invalideopÃ©rande mÃ©moire invalidemauvaise taille de fusion d'entitÃ©mode invalideregistre d'adresse movx invalideregistre dsp movx invalideregistre d'adresse movy invalideregistre dsp movy invalidesuffixe nÃ©on invalide pour une instruction non nÃ©onnombre invalidenombre de registres invalide dans la liste, %d registres sont attendus Ã l'opÃ©rande %d â€” Â«Â %sÂ Â»nombre de registres invalide dans la liste, seulement 1 registre est attendu Ã l'opÃ©rande %d â€” Â«Â %sÂ Â»expression d'offset invalideoffset invalide, cible n'est pas alignÃ©e sur une frontiÃ¨re de mot (0x%08lX)offset invalide, valeur trop grande (0x%08lX)opcode invalideopcode Â«Â %sÂ Â» invalide dans la rÃ¨gle de transition Â«Â %sÂ Â»opcode invalide, Â«Â %sÂ Â».opÃ©rande invalideopÃ©rande invalide (section %s) pour Â«Â %sÂ Â»opÃ©rande invalide (section %s) pour Â«Â %sÂ Â» en dÃ©finissant Â«Â %sÂ Â»opÃ©rande invalide dans ldmopÃ©rande invalide dans stmmode d'opÃ©rande invalide pour cette architecture; a besoin de 68020 ou plusopÃ©rande invalide ()+opÃ©rande invalide -()opÃ©rande invalide de S^#mauvaise taille d'opÃ©rande demandÃ©esuffixe d'opÃ©rande invalideopÃ©rande invalide pour la directive .code (%d) (attendu 16 ou 32)opÃ©rande invalide pour l'opcode %s: Â«Â %sÂ Â»opÃ©rande invalide n'est pas une valeur signÃ©e de 10 bits: %dvaleur de l'opÃ©rande n'est pas une valeur signÃ©e de 11 bits: %dopÃ©rande invalide n'est pas une valeur signÃ©e de 12 bits: %dopÃ©rande invalide n'est pas une valeur signÃ©e de 13 bits: %dopÃ©rande invalide n'est pas une valeur signÃ©e de 16 bits: %dopÃ©rande invalide n'est pas une valeur non signÃ©e de 16 bits: %dvaleur de l'opÃ©rande n'est pas une valeur non signÃ©e de 5 bits: %dvaleur de l'opÃ©rande n'est pas une valeur non signÃ©e de 6 bits: %dvaleur de l'opÃ©rande n'est pas une valeur non signÃ©e de 6 bits: %dopÃ©rande invalide, n'est pas un multiple de 32: %dopÃ©rande invalide, n'est pas un multiple de 4: %dopÃ©rande invalide, n'est pas un multiple de 8: %dopÃ©rande invalide n'est pas une valeur paire: %dopÃ©rande invalide: expression dans la cible PTopÃ©randes invalidesopÃ©randes invalides (sections %s et %s) pour Â«Â %sÂ Â»opÃ©randes invalides (sections %s et %s) pour Â«Â %sÂ Â» en dÃ©finissant Â«Â %sÂ Â»opÃ©randes invalide pour l'op cross-unitopÃ©randes invalides pour opcodeopÃ©randes invalides vers %sopÃ©randes invalides pour l'opcode %s: Â«Â %sÂ Â»encodage invalide ou non supportÃ© dans .cfi_lsdaencodage invalide ou non supportÃ© dans .cfi_personalityadresse relative au PC invalideregistre de performance invalidenom d'opÃ©ration pref invalideprioritÃ© Â«Â %luÂ Â» invalidepseudo opÃ©ration invalidele registre quickrot spÃ©cifiÃ© est invalidel'unitÃ© quickrot spÃ©cifiÃ©e est invalidelimite invalide dans la liste des registres vectorielsregistre invalideregistre %s invalideregistre Â«Â %sÂ Â» invalide pour l'instruction Â«Â %sÂ Â»expression de registre invalideregistre invalide pour l'accÃ¨s mÃ©moireliste de registres invalideliste de registres invalide pour les instructions push/popmasque de registre invalidenom de registre invalidenumÃ©ro de registre invalide (%ld) pour Â«Â %sÂ Â»numÃ©ro de registre invalide (%ld) pour l'instruction Â«Â %sÂ Â»numÃ©ro de registre invalide: %d n'est pas dans [r0--r7]opÃ©rande registre invalideopÃ©rande nÂ°1 de registre invalideopÃ©rande nÂ°2 de registre invalideopÃ©rande nÂ°3 de registre invalideopÃ©rande nÂ°4 de registre invalideopÃ©rande de registre invalideÂ : %splage de registre invalidetype de registre %d invalideregistre invalide: r15 illÃ©galrÃ©sultat de relÃ¢che de fragment invalideexpression de rÃ©adressage invaliderÃ©adressage invaliderÃ©adressage %s invalide pour le champexpression de rÃ©adressage invaliderÃ©adressage invalide pour l'instruction Â«Â %sÂ Â»rÃ©adressage invalide pour le champrÃ©adressage invalide pour l'instructionrÃ©adressage invalide pour l'opÃ©rande %d de Â«Â %sÂ Â»rÃ©adressage invalide pour l'opÃ©rande %i de Â«Â %sÂ Â»rÃ©adressage invalide dans la position d'instruction %irotation invalidemode d'arrondi incorrectregistre scalaire invalide dans la listefacteur d'Ã©chelle invalidesegment invalide Â«Â %sÂ Â»dÃ©calage invalidedÃ©calage invalide pour le mode d'adressage de l'offset du registreopÃ©rateur de dÃ©calage invalidevaleur de dÃ©calage illÃ©gale: %ldforme courte d'un opÃ©rande immÃ©diat en virgule flottante invalideexpression smc invalideopÃ©rande de mÃ©moire source invalideregistre source invalideliste de registres source invalideunitÃ© source invalidesuffixe invalidesuffixe invalide aprÃ¨s le registre.expression swi invalideoption invalide -m%sopÃ©rande symbolique invalidesyntaxe invalide pour le directive .dnsyntaxe invalide pour le directive .qnsyntaxe invalide pour le directive .reqsyntaxe invalide pour le directive .unreqnom de registre systÃ¨me invalideversion matÃ©rielle cible invalidetype invalide pour le bassin de littÃ©ralesvaleur d'opÃ©rande non Ã©tendue invalideopcode unwind incorrectutilisation invalide de Â«Â =immediateÂ Â»utilisation invalide du rÃ©adressage %sutilisation invalide de Â«Â MSLÂ Â»utilisation invalide de Â«Â MULÂ Â»utilisation invalide d'un dÃ©calage de registre 32 bitsutilisation invalide d'un dÃ©calage de registre 64 bitsutilisation invalide de l'opÃ©rateur Â«Â %sÂ Â»mauvaise utilisation d'un registre vectorielvaleur invalide pour un registre Ã usage spÃ©cialregistre vectoriel invalide dans la listenom de registre vectoriel invalidemasque d'Ã©criture Â«Â %sÂ Â» invalidemasque de zÃ©rotage Â«Â %sÂ Â» invalidevaleur de is_stmt n'est pas 0 ou 1le numÃ©ro isa est plus petit que unsaut pas Ã 3..10 octets (est %d)cible du saut hors limitecible du saut hors limite; aucun trampoline adÃ©quat trouvÃ©saut vers un symbole dans un autre mode ISAsaut vers une adresse mal alignÃ©e (0x%lx)rebuts Â«Â %sÂ Â» aprÃ¨s l'expressionrebut Â«Â %sÂ Â» aprÃ¨s le registrerebut aprÃ¨s l'opÃ©rande %u de Â«Â %.*sÂ Â»rebut Ã la fin de la ligne, premier caractÃ¨re non reconnu est Â«Â %cÂ Â»rebut Ã la fin de la ligne, premier caractÃ¨re non reconnu Ã©valuÃ© en 0x%xrebut Ã la fin de la ligne: Â«Â %sÂ Â»rebut Ã la fin de la ligne: Â«Â %sÂ Â»rebut Ã la fin de la chaÃ®ne de machine, le premier caractÃ¨re non reconnu est Â«Â %cÂ Â»rebut trouvÃ© aprÃ¨s l'instructionÂ : %s.%sÂ«Â laÂ Â» doit Ãªtre utilisÃ© avec un symbole. Â«Â %sÂ Â»la utilisÃ© pour charger une adresse 64 bits; il est recommandÃ© d'utiliser dlaÃ©tiquette Â«Â $%dÂ Â» redÃ©finieÃ©tiquette Â«Â %d$Â Â» redÃ©finiel'Ã©tiquette Â«Â %sÂ Â» n'a pas Ã©tÃ© dÃ©finie dans cette section dwarfÃ©tiquette aprÃ¨s Â«Â ||Â Â»Ã©tiquette aprÃ¨s le prÃ©dicatÃ©tiquette pas au dÃ©but du paquet d'exÃ©cutionles Ã©tiquettes ne sont pas valables dans des paquetsÃ©tiquette manquanteÃ©tiquette manquante dernier registre doit Ãªtre r7ldr vers le registre 15 doit Ãªtre alignÃ© sur 4 octetsldrd/strd exige une paire de registre paire:impairel'opÃ©rande leb128 est un symbole indÃ©fini: %sopÃ©rande de gauche est un grand nombre; entier 0 assumÃ©opÃ©rande de gauche est un nombre flottant; entier 0 assumÃ©longueur n'est pas nÃ©cessairelongueur de .comm Â«Â %sÂ Â» est dÃ©jÃ %ld. N'a pas Ã©tÃ© changÃ© pour %ld.longueur de .lcomm Â«Â %sÂ Â» est dÃ©jÃ %ld. N'a pas Ã©tÃ© changÃ© Ã %ld.Ã©tiquette li rd n'est pas une forme d'instruction correcteligne %d: rep ou repi doit inclure au moins 4 instructionsligne %d: incapable d'insÃ©rer l'adresse du symbole Â«Â %sÂ Â» dans un octetligne %d: incapable d'insÃ©rer l'adresse du symbole Â«Â %sÂ Â» dans un quadligne %d: incapable d'insÃ©rer l'adresse du symbole Â«Â %sÂ Â» dans un shortligne %d: incapable d'insÃ©rer la valeur %lx dans un octetligne %d: incapable d'insÃ©rer la valeur %lx dans un shortligne %d: type de rÃ©adressage inconnu: 0x%xnumÃ©ro de ligne (%d) pour la directive .stab%c ne peut s'insÃ©rer dans le champ d'index (20 bits)numÃ©ros de lignes doivent Ãªtre positifs; numÃ©ro de ligne %d rejetÃ©le registre de lien doit Ãªtre dans un registre avec un numÃ©ro basl'unitÃ© de registre de lien doit Ãªtre parmi %sinsertion dans le pool littÃ©ral a Ã©chouÃ©position de bassin de littÃ©raux requise avec text-section-literals; spÃ©cifiÃ© le avec .literal_positiondÃ©bordement du pool de littÃ©rauxlittÃ©ral rÃ©fÃ©rencÃ© Ã travers une frontiÃ¨re de sectionmode d'adressage lk sont invalides pour un mode d'adressage par registre adressant la mÃ©moirela pseudo instruction lmi ne devrait pas utiliser une Ã©tiquette dans le champ immregistre LO requisrÃ©adressage lo() utilisÃ© sur une instruction qui ne le supporte paschargement du mÃªme registre dans une opÃ©ration parallÃ¨leÃ©tiquette locale Â«Â %sÂ Â» n'est pas dÃ©finielong saut (jump) requisune boucle contenant moins de trois instructions peut dÃ©clencher un errata matÃ©riella constante de dÃ©compte de boucle %ld est hors des limites [1..%d]la fin d'une boucle trop proche de la fin d'une autre boucle peut dÃ©clencher un errata matÃ©rialboucle cible ne rÃ©fÃ¨re pas Ã une instruction de boucle dans la sectionboucle trop longue pour l'instruction LOOPboucle: dÃ©placement 32 bits non supportÃ©registre infÃ©rieur (r0-r15) attendu, pas '%.100s'16 bits infÃ©rieurs du masque sont ignorÃ©sl'expression lui n'est pas dans les bornes 0..1048575fonctionnalitÃ©s m68k et cf sÃ©lectionnÃ©es toutes les deuxmacro %s n'est pas encore implÃ©mentÃ©el'instruction macro a Ã©tÃ© Ã©tendue dans une instruction de mauvaise taille dans un slot d'un branchement 16 bits diffÃ©rÃ©l'instruction macro a Ã©tÃ© Ã©tendue dans une instruction de mauvaise taille dans un slot d'un branchement 32 bits diffÃ©rÃ©instruction macro Ã©tendue en de multiples instructionsl'instruction macro a Ã©tÃ© Ã©tendue en de multiples instructions dans un emplacement de branchement diffÃ©rÃ©macro requiert le registre $at alors qu'il n'est pas effectifmacro requiert $at alors que $at est utilisÃ©macro utilisÃ©e $at aprÃ¨s ".set noat"macros imbriquÃ©es trop profondÃ©mentl'opcode majeur n'est pas triÃ© pour %sl'opcode majeur n'est pas dans la plage [0x%02x - 0x%02x]liste de registre mal formÃ©e dans push/popmasque pas sur un opÃ©rande de destinationle masque Ã©lague les bits de l'opcode pour %sregistres masque, index et de destination doivent Ãªtre distinctsregistres masque, index et de destination devraient Ãªtre distinctsopÃ©randes correspondants au opcodemd_apply_fix: r_type 0x%x inconnu md_estimate_size_before_relax destination mÃ©moire nÃ©cessaire pour l'instruction Â«Â %sÂ Â» aprÃ¨s Â«Â xreleaseÂ Â»l'opcode mineur n'est pas dans la plage [0x00 - 0x3f]destination de branchement mal alignÃ©edonnÃ©es mal alignÃ©esdÃ©calage dÃ©salignÃ©pas de concordance entre la taille du opcode et celle de l'opÃ©randepas de concordance entre le registre et le suffixenon concordance du format Â«Â %sÂ Â»: #slots = %d, #opcodes = %d.eb ne concorde pastypes d'Ã©lÃ©ment/structure en dÃ©saccord dans la listeparenthÃ¨ses non concordantes.procend mal positionnÃ©opÃ©rande PIC mal positionnÃ©Â«Â %cÂ Â» manquantÂ«Â )Â Â» manquantÂ«Â ]Â Â» manquant+ manquant.end manquant.end manquant Ã la fin de l'assemblage.end ou .bend manquant Ã la fin du fichier.endp manquant avant .cfi_startproc.fnstart manquant avant la directive de dÃ©roulement.func manquant.proc manquant= manquantfanions CPS manquantsnom de DSP manquant Â«Â %sÂ Â»[ manquant] manquantÂ«Â )Â Â» manquanteÂ«Â )Â Â» manquante aprÃ¨s les paramÃ¨tres formels dans la dÃ©finition de la macro Â«Â %sÂ Â»Â«Â .endÂ Â» manquantÂ«Â ]Â Â» manquantÂ«Â lockÂ Â» manquant avec Â«Â %sÂ Â»Â«Â }Â Â» manquantÂ«Â }Â Â» manquante dans Â«Â %sÂ Â»nom d'abi manquant Â«Â %sÂ Â»alignement manquantindice d'alignement manquantextension d'architecture manquantenom d'architecture manquante Â«Â %sÂ Â»argument manquantargument manquant pour la directive %s_checksÃ©parateur d'argument Â«Â ,Â Â» manquant pour .cpsetuptype de bloc manquantdÃ©compte de break manquantargument d'appel manquantsignature d'appel manquanteclasse manquanteapostrophe de fermeture manquant; (assumÃ©)Â«Â "Â Â» fermant manquantÂ«Â %cÂ Â» fermant manquantaccolade fermante manquanteparenthÃ¨ses fermante manquantevirgule manquantevirgule manquante aprÃ¨s la constante de insn virgule ou deux-point manquantcode de condition manquant dans la directive de contrÃ´le structurÃ©earchitecture cpu manquantenom de cpu manquant Â«Â %sÂ Â»Â«Â doÂ Â» manquanttaille d'Ã©lÃ©ment manquantenom du mode d'Ã©mulation manquantapostrophe de fin manquantexpression manquanteexpression manquante dans la directive .abiversionexpression manquante dans la directive .localentryexpression manquante dans la directive .sizefanions manquants: Â«Â PÂ Â», Â«Â NÂ Â» ou Â«Â ZÂ Â» requisnom de fpu manquant Â«Â %sÂ Â»taille de cadre manquanteexpression immÃ©diate manquanteÃ©tiquette manquanteexpression locale manquanteindex local manquantparamÃ¨tre du modÃ¨le manquantnom manquantdÃ©calage manquantoffset manquant dans l'adressage prÃ© indexÃ©opcode manquantopÃ©rande manquantopÃ©rande manquant aprÃ¨s la virguleopÃ©rande manquant; zÃ©ro assumÃ©expression d'offset manquante ou erronÃ©eexpression de dÃ©placement manquante ou invalide Â«Â %sÂ Â»expression de dÃ©placement invalide ou manquante Â«Â %sÂ Â» alors 0 est assumÃ© Ã sa placeexpression manquante ou invalide Â«Â %sÂ Â»expression immÃ©diate manquante ou invalide Â«Â %sÂ Â»type de prÃ©dicat manquantnom de symbole rÃ©el manquanttype de rÃ©adressage manquantchaÃ®ne renommÃ©e manquanteargument rÃ©servÃ© de current_memory/grow_memory manquantchamp de rotation manquant aprÃ¨s la virgulesÃ©parateur manquantlongueur de dÃ©calage manquantetaille manquanteexpression de la taille manquanteexpression sizeof_stub manquantechaÃ®ne manquantenom de symbole manquantindex de table manquantÂ«Â thenÂ Â» manquantÂ«Â toÂ Â» ou Â«Â downtoÂ Â» manquanttype manquantsuffixe de type manquantvaleur manquantenom de version manquant dans Â«Â %sÂ» pour le symbole Â«%sÂ Â»plus de 65K de mots dans le bassinmov ne peut utiliser un port RD comme destinationÂ«Â ||Â Â» multiples sur la mÃªme lignebranchements ou sauts multiples dans le mÃªme paquetspÃ©cifications multiples de conditionmultiples noms d'Ã©mulation spÃ©cifiÃ©splusieurs formats spÃ©cifiÃ©s pour un paquet: utilise Â«Â %sÂ Â»littÃ©raux multiples dans l'expansionspÃ©cifications multiples movxspÃ©cifications multiples movyspÃ©cifications multiples de traitement parallÃ¨lemultiples prÃ©dicats sur la mÃªme lignemultiples sections remappÃ©s vers la section de sortie %sversions multiples [Â«%sÂ»|Â«%sÂ»] pour le symbole Â«%sÂ»Ã©critures multiples dans le mÃªme registredoit Ãªtre @(r0,...)vous devez spÃ©cifier les extensions Ã ajouter avant celles Ã retirerun qualificatif PIC est requis avec un symbole.un qualificatif PIC est requis avec le symbole. Â«Â %sÂ Â»@GOT ou @GOTOFF requis. %salignement nÃ©gatifcompteur nÃ©gatif pour %s â€“ ignorÃ©edÃ©calage nÃ©gatiftaille nÃ©gativevaleur nÃ©gative ignorÃ©e dans %saucun opcode Power ou PowerPC n'a Ã©tÃ© sÃ©lectionnÃ©.blocs .bs imbriquÃ©sdirective .ent imbriquÃ©esboucle pipelinÃ©e par le logiciel imbriquÃ©esaut de ligne dans le titrenouvelle section Â«Â %sÂ Â» dÃ©finie sans attributs - cela pourrait causer des problÃ¨mesÂ«Â nextÂ Â» en dehors de la boucle structurÃ©epas de rÃ©adressage sur %d octetspas de Â«Â (Â Â» correspondant Ã Â«Â )Â Â»pas de Â«Â [Â Â» correspondant Ã Â«Â ]Â Â»pas de pseudo-op .cprestore utilisÃ© dans le code PICpas de pseudo-op .frame utilisÃ© dans le code PICaucune architecture ne contient toutes les instructions utilisÃ©es pas compilÃ© avec le support pour x86_64 32 bitspas compilÃ© pour le support de format de fichier objet de 64 bitspas compilÃ© avec le support pour x86_64aucun pointeur de fichier courantpas de symbole d'entrÃ©e pour la fonction globale Â«Â %sÂ Â»aucun nom de fichier aprÃ¨s l'option -taucun nom de fichier aprÃ¨s le pseudo-op .INCLUDEpas d'unitÃ© en virgule flottante spÃ©cifiÃ©epas de type de fonction pour le rÃ©adressage PLTpas d'entrÃ©e hppa_fixup entry pour le correctif du type 0x%xaucun suffixe de mnÃ©monique d'instruction fourni et pas d'opÃ©rande registre; ne peut dÃ©terminer la taille de l'instructionaucun suffixe de mnÃ©monique d'instruction fourni; ne peut dÃ©terminer la taille de l'immÃ©diataucune section dwarf XCOFF connue pour le fanion 0x%08x pas de section prÃ©cÃ©dente pour y retourner, ignorÃ©e.pas de fragment enregistrÃ© pour le littÃ©ralaucune relaxation trouvÃ©e pour cette instruction.pas de numÃ©ro de sÃ©quence aprÃ¨s !%spas de modificateur de taille aprÃ¨s le point, .w assumÃ©pas de tel modificateur d'architecture: Â«Â %sÂ Â»pas de telle architecture: Â«Â %sÂ Â»pas de telle instruction: Â«Â %sÂ Â»pas de telle extension machine Â«Â %sÂ Â»pas de tel Â«Â sfrÂ Â» pour cette architecturepas de dÃ©finition GREG satisfaisante pour les opÃ©randespas d'Ã©tiquette spÃ©cifiÃ©e pour %spas de faÃ§on de traiter .file Ã l'intÃ©rieur d'une section .ent/.endno-auto-litpools est incompatible avec auto-litpool-limitsaut non PIC utilisÃ© dans la librairie PICexpression non absolue dams le champ de constantevaleur non absolue utilisÃ©e avec .space/.bes.%cleb128 non constant n'est pas supportÃ©compteur d'octet n'est pas une constanteexpression n'est pas une constante dans la dÃ©claration Â«Â .elseifÂ Â»expression n'est pas une constante dans la dÃ©claration Â«Â .ifÂ Â»dÃ©compte de remplissage non constant dans une section absoluegame de registres non contiguÃ«opÃ©rande OPF n'est pas immÃ©diat, ignorÃ©rÃ©adressage non relatif au PC pour un champ relatif au PCn'est pas une instruction de 16 bits Â«Â %sÂ Â»pas assez d'opÃ©randes (%d) pour Â«Â %sÂ Â»; attendu %daucun registre de base utilisÃ©nombre (0x%s) plus grand que 32 bitsnombre plus grand que 64 bitsle nombre doit Ãªtre positif et plus petit que %dnombre de jetons littÃ©raux != 1non concordance du nombre d'opÃ©randesLe nombre de registres doit Ãªtre compris dans l'intervalle [1:4]une vue numÃ©rique peut uniquement Ãªtre affirmÃ©e Ã zÃ©roopÃ©rande d'adresse impaire: %lddÃ©placement impair Ã %xdistance impaire de branchement (0x%lx octet)distance impaire de branchement (0x%lx octets)nombre impaire ne peut Ãªtre utilisÃ© icinombre impair d'octets dans la description de l'opÃ©randeregistre gÃ©nÃ©ral impaire spÃ©cifiÃ© comme paire de registresregistre impaire ne peut Ãªtre utilisÃ© icioffset et base doivent provenir de la mÃªme unitÃ©le dÃ©calage Ã une taille diffÃ©rente de la basel'offset dans l'opÃ©rande %u de Â«Â %.*sÂ Â» n'est pas divisible par %ul'offset dans l'opÃ©rande %u de Â«Â %.*sÂ Â» est hors limitel'offset doit Ãªtre un multiple de %dl'offset doit Ãªtre zÃ©ro dans l'encodage ARMl'offset n'est pas un multiple de 4offset hors limiteregistre de dÃ©calage attendudÃ©calage vers une destination non alignÃ©edÃ©calage d'adresse trop grandvaleur d'offset hors limiteseul le dÃ©calage Â«Â LSLÂ Â» est permisseul Â«Â MUL VLÂ Â» est permisseul Â«Â MULÂ Â» est permisseulement les registres D peuvent Ãªtre indexÃ©sseul le dÃ©calage LSL est permis en mode thumbseulement SUBS PC, LR, #const permisseule une expression constante est permiseseul des constantes de dÃ©calage sont supportÃ©es dans une section absolueseul le zÃ©ro en virgule flottante est autorisÃ© comme valeur immÃ©diateseul les registres lo sont permis avec un immÃ©diatseuls les 16 bits infÃ©rieurs du premier opÃ©rande sont utilisÃ©sun type seulement devrait Ãªtre spÃ©cifiÃ© pour l'opÃ©randeseul r0 peut Ãªtre utilisÃ© comme registre de dÃ©compte d'octetseul le champs d'octet r0.bX de r0 peut Ãªtre utilisÃ© comme dÃ©compte d'octetseul r15 est permis iciseuls des types de blocs uniques sont permisuniquement supportÃ© avec un ancien gccseuls deux registres consÃ©cutifs VFP SP sont permis iciopcode %s pas trouvÃ© dans la table de hachage des opcodesl'opcode Â«Â %sÂ Â» n'est pas supportÃ© pour la cible %sopcode Â«Â %sÂ Â»: ne peut trouver la dÃ©finition littÃ©raleopcode Â«Â %sÂ Â»: n'a pu analyser l'opÃ©rande Â«Â %sÂ Â» dans Â«Â %sÂ Â»opcode Â«Â %sÂ Â»: pas d'opnom liÃ© Â«Â %sÂ Â» pour la prÃ© condition dans Â«Â %sÂ Â»opcode Â«Â %sÂ Â»: la prÃ© condition contient seulement des constantes dans Â«Â %sÂ Â»opcode Â«Â %sÂ Â»: le remplaÃ§ant n'a pas %d opopcode Â«Â %sÂ Â»: le remplaÃ§ant n'a pas %d opsopcode Â«Â %sÂ Â»: opÃ©rande Â«Â %sÂ Â» non identifiÃ© dans Â«Â %sÂ Â»opcode Â«Â NOP.NÂ Â» non disponible dans cette configurationopcode Â«Â %sÂ Â» n'est pas supportÃ© pour la cible %sopcode n'a pas d'effetopcode manquant ou pas trouvÃ© sur la ligne d'entrÃ©eopcode non supportÃ© en mode Â«Â insn32Â Â»opcode non supportÃ© dans le mode Â«Â insn32Â Â» Â«Â %sÂ Â»opcode non supportÃ© sur ce processeur: %s (%s)opcode pas valable pour cette variante de cpule rÃ©adressage spÃ©cifique Ã un opcode %s est utilisÃ© en dehors d'une instructionles opcodes Â«Â %sÂ Â» (emplacement %d) et Â«Â %sÂ Â» (emplacement %d) ont tous les deux des accÃ¨s de ports volatilesles opcodes Â«Â %sÂ Â» (emplacement %d) et Â«Â %sÂ Â» (emplacement %d) Ã©crivent dans le mÃªme portles opcodes Â«Â %sÂ Â» (emplacement %d) et Â«Â %sÂ Â» (emplacement %d) Ã©crivent dans le mÃªme registreles opcodes Â«Â %sÂ Â» (emplacement %d) et Â«Â %sÂ Â» (emplacement %d) Ã©crivent dans le mÃªme Ã©tatouverture CFI Ã la fin du fichier; directive .cfi_endproc manquanteopÃ©randel'opÃ©rande %d doit Ãªtre %s â€” Â«Â %sÂ Â»opÃ©rande %d doit Ãªtre un immÃ©diatl'opÃ©rande %d doit Ãªtre une expression immÃ©diatel'opÃ©rande %d doit Ãªtre une constanteopÃ©rande %d doit Ãªtre scalairel'opÃ©rande %d doit Ãªtre le mÃªme registre que l'opÃ©rande 1 â€” Â«Â %sÂ Â»opÃ©rande %d de Â«Â %sÂ Â» a une valeur Â«Â %uÂ Â» invalideopÃ©rande %d de Â«Â %sÂ Â» a une valeur Â«Â %uÂ Â» hors limiteopÃ©rande %d hors limiterecouvrement de l'opÃ©rande %d dans %sopÃ©rande %d: expression use illÃ©gale: Â«Â %sÂ Â»opÃ©rande %s0x%lx hors limite.opÃ©rande %u de Â«Â %.*sÂ Â» est en lecture seuleopÃ©rande %u de Â«Â %.*sÂ Â» est en Ã©criture seuleopÃ©rande %u de Â«Â %.*sÂ Â» n'est pas un registre de base valideopÃ©rande %u de Â«Â %.*sÂ Â» n'est pas une rÃ©fÃ©rence mÃ©moire valideopÃ©rande %u de Â«Â %.*sÂ Â» n'est pas valide comme registre d'adresse de retouropÃ©rande %u de Â«Â %.*sÂ Â» n'est pas une constanteopÃ©rande %u de Â«Â %.*sÂ Â» du mauvais cÃ´tÃ©l'opÃ©rande %u de Â«Â %.*sÂ Â» est hors limiteopÃ©rande 1 doit Ãªtre FPSCRerreur d'index d'opÃ©rande pour %sl'opÃ©rande n'est pas une constante absolueopÃ©rande n'est pas un immÃ©diatdÃ©bordement du masque de l'opÃ©randeopÃ©randes ne concordent pas â€” Â«Â %sÂ Â»l'opÃ©rande doit Ãªtre une constantel'opÃ©rande doit Ãªtre une constante ou une Ã©tiquetteopÃ©rande doit Ãªtre un multiple de 2opÃ©rande doit Ãªtre un multiple de 4opÃ©rande doit Ãªtre absolu dans les bornes %lx..%lx et non pas %lxopÃ©rande doit Ãªtre absolu dans les bornes %u..%u et non pas %ldopÃ©rande n'est pas un multiple de 4 pour PT, PTA ou PTB: %dnombre d'opÃ©randes ne concordent pasopÃ©rande hors limiteopÃ©rande hors limite (%d n'est pas entre %d et %d)opÃ©rande hors limite (%s n'est pas entre %ld et %ld)opÃ©rande hors limite pour PT, PTA et PTBopÃ©rande hors limite, instruction a Ã©tÃ© Ã©tendueopÃ©rande hors limite: %ldopÃ©rande hors limite: %luopÃ©rande hors limite: 0x%lxdÃ©bordement de l'opÃ©randel'opÃ©rande rÃ©fÃ©rence R%ld de l'instruction avant la prÃ©cÃ©dente.l'opÃ©rande rÃ©fÃ©rence R%ld de l'instruction prÃ©cÃ©dente.l'opÃ©rande rÃ©fÃ©rence le R%ld du chargement prÃ©cÃ©dent.non concordance de la taille d'opÃ©randela taille de l'opÃ©rande doit Ãªtre spÃ©cifiÃ©e pour VMOV immÃ©diatla taille de l'opÃ©rande doit correspondre Ã la largeur du registrenon concordance du type d'opÃ©randeles types de l'opÃ©rande ne peuvent pas Ãªtre infÃ©rÃ©svaleur d'opÃ©rande hors limite pour l'instructiontailles/opÃ©randes ne concordent pasopÃ©randes 0 et 1 doivent Ãªtre le mÃªme registreopÃ©randes pour l'opcode Â«Â %sÂ Â» ne correspondent Ã aucun format valableopÃ©randes ne concordent pasopÃ©randes n'Ã©taient pas rÃ©ductibles au moment de l'assemblageoperation combine des symboles dans diffÃ©rents segmentsl'option --link-relax est seulement supportÃ©e dans le format b.outl'option Â«Â %sÂ Â» ne peut pas Ãªtre inversÃ©eoption Â«Â %sÂ Â» n'est pas reconnueoption Â«Â -%c%sÂ Â» est dÃ©prÃ©ciÃ©e: %soption Â«Â -A%sÂ Â» est dÃ©prÃ©ciÃ©e: utilisez Â«Â -%sÂ Â»ou plusmÃ©moire Ã©puisÃ©ehors limiteafficher des messages d'erreur verbeuxdÃ©bordementdÃ©bordement durant le branchement vers %s; converti en une sÃ©quence d'instructions plus longuedÃ©bordement dans l'argument immÃ©diatdÃ©bordement dans la table de littÃ©raux (.lit8)dÃ©bordement dans la table de littÃ©raux (.lita)p2align n'est pas supportÃ© pour cette cibleconflit d'empaquetage: %s doit Ãªtre soumis sÃ©quentiellementbourrage ajoutÃ©parallÃ¨lel'instruction parallÃ¨le ne suit pas une autre instructionparenthÃ¨ses ignorÃ©eserreur d'analysePC ne peut Ãªtre utilisÃ© en mode rÃ©Ã©criturerelatif au PC offset d'adresse relatif au PC est hors limiteoffset de chargement relatif au PC n'est pas alignÃ© sur un motoffset de chargement relatif au PC est hors limiteerreur d'instruction pce (16 bits || 16 bits).pcrel pour branchement vers %s est trop loin (0x%lx)pcrel pour branchement vers %s est trop loin (0x%x)pcrel pour loopt est trop Ã©loignÃ© (0x%lx)pcrel pour lrw/jmpi/jsri vers %s est trop loin (0x%lx)rÃ©adressage pcrel pas permis dans une instructionpcrel trop Ã©loignÃ©pcrel trop Ã©loignÃ© BFD_RELOC_BFIN_10pcrel trop Ã©loignÃ© BFD_RELOC_BFIN_11_PCRELpcrel trop Ã©loignÃ© BFD_RELOC_BFIN_12pcrel trop Ã©loignÃ© BFD_RELOC_BFIN_24pcrel trop Ã©loignÃ© BFD_RELOC_BFIN_5pcrel trop loin BFD_RELOC_MOXIE_10routine de personnalitÃ© requise avant la directive .handlerdataroutine de personnalitÃ© spÃ©cifiÃ©e dans un cadre cantunwindregistre de pointeur (X, Y ou Z) requisregistre de pointeur (Y ou Z) requisregistre de pointeur Z requisles polymorphes ne sont pas activÃ©s. Utilisez l'option -mP pour l'activer.le post-index doit Ãªtre un registreexpression post-indexÃ©e utilisÃ©e dans une instruction de prÃ©chargementpost-incrÃ©mentation pas supportÃ©epowerpc_operands[%d] double powerpc_operands[%d]powerpc_operands[%d].bitm invalideinstruction pre-indexÃ©e attenduele prÃ©dicat n'est pas suivi d'une instruction.prÃ©dicat sur A0 n'est pas supportÃ© sur cette architectureprefer-const16 entre en conflit avec prefer-l32rprefer-l32r entre en conflit avec prefer-const16fin prÃ©maturÃ©e d'un prÃ©fixe virgule flottante.ent prÃ©cÃ©dent pas fermÃ© par un .endentrÃ©e CFI prÃ©cÃ©dente n'est pas fermÃ© (.cfi_endproc manquant)le movx prÃ©cÃ©dent exige nopyle movy prÃ©cÃ©dent exige nopxprofilage dans une section absolue ?la pseudo instruction Â«Â %sÂ Â» n'est pas supportÃ©epseudo prÃ©fixe sans instructionpseudo-op illÃ©gal Ã l'intÃ©rieur de .struct/.unionpush/pop ne supporte pas {reglist}^le prÃ©dicat qualifiant n'est pas suivi d'une instructionoffset de branchement rapide %d hors des limites %d Ã %dr12 n'est pas permis icir13 n'est pas permis icir14 n'est pas permis comme premier registre quand le second registre est omisr14 n'est pas permis icir15 utilisÃ© comme registre de base de stockage n'est pas permisr15 n'est pas permis icir2 ne devrait pas Ãªtre utilisÃ© en mode d'adressage indexÃ©r31 ne peut pas Ãªtre utilisÃ© avec jmp; utilisez ret Ã la placer31 ne peut pas Ãªtre utilisÃ© avec jmpr.n; utilisez ret.n Ã la placerd doit Ãªtre un nombre paire.rdhi et rdlo doivent Ãªtre diffÃ©rentsrdhi, rdlo et rm doivent tous Ãªtre diffÃ©rentscode rÃ©entrantle type d'enregistrement n'est pas valabletype_enregistrement_invalidesymbole redÃ©fini ne peut Ãªtre utilisÃ© sur un rÃ©adressageredÃ©finition du registre globalredÃ©finition du type MCU Â«Â %sÂ Â» en Â«Â %sÂ Â»prÃ©fixe %s redondantreg devrait Ãªtre <= 31reg-reg attenduregistre attenduregistre attendu, mais a eu '%.6s'registre attendu, pas '%.100s'registre hors ordreregistre de mauvaise taille pour le mot %sregistre de mauvaise taille pour l'adresse %sla liste doit contenir un nombre paire de registresla liste de registres doit provenir de la mÃªme unitÃ©une liste de registres doit contenir au moins 1 registre et au plus 16 registresla liste des registres ne doit pas contenir de doublonsliste de registres n'est pas en ordre croissantle registre doit Ãªtre soit sp ou soit spÃ©cifiÃ© par une directive unwind_movsp prÃ©cÃ©dentenom de registre ou numÃ©ro de registre 0 Ã 31 requisnom de registre ou numÃ©ro de registre 16 Ã 31 requisle registre numÃ©ro %u n'est pas supportÃ© sur cette architecturenumÃ©ro de registre au-dessus de 15 requisnumÃ©ro de registre hors limitenumÃ©ro de registre trop grand pour push/pople dÃ©calage de registre n'est pas permis en mode d'adressage prÃ© indexÃ©opÃ©rande de registre attendu mais on a trouvÃ© un scalaireregistre hors limite dans la listepaire de registre pour l'opÃ©rande %u de Â«Â %.*sÂ Â» n'est pas une paire pair/impair valideregistre r%d hors limiteregistre r0 ne peut Ãªtre utilisÃ© iciregistres r16-r23 requisregistre r24, r26, r28 ou r30 requisgamme de registres n'est pas en ordre croissantregistre rh%d hors limiteregistre rl%d hors limiteregistre rq%d n'existe pasregistre rq%d hors limiteregistre rr%d n'existe pasregistre rr%d hors limiteregistre identique Ã la base de rÃ©Ã©crituredÃ©calage de sauvegarde du registre n'est pas un multiple de %ula mise Ã l'Ã©chelle du registre est ignorÃ©e icisection de registre a un contenu pas des registres doit Ãªtre 1 ou 2syntaxe du registre est .register %%g[2367],{#scratch|symbolname|#ignore}non concordance du type de registrel'unitÃ© de registre doit Ãªtre parmi %svaleur de registre utilisÃ©e comme expressionles registres ne peuvent pas Ãªtre les mÃªmesrel trop Ã©loignÃ© BFD_RELOC_16rel trop Ã©loignÃ© BFD_RELOC_8dÃ©bordement de rÃ©adressage rel31adresse relative hors limiteappel relatif hors limitesaut relatif hors limiteinstruction non reconnue dans indice de relaxation: ligne %d.relaxation non supportÃ©e relÃ¢che d'un branchement hors limite dans le saut (jump)rÃ©adressage %d n'est pas supportÃ© dans le format du fichier objetrÃ©adressage n'est pas dans une (partie corrigÃ©e de) sectionle champ relocalisÃ© et le type relocalisÃ© diffÃ¨rent sur le signerÃ©adressage %s n'est pas supportÃ© par l'ABI actuellerÃ©adressage ne peut Ãªtre fait avec -mrelocatablele rÃ©adressage n'est pas supportÃ©rÃ©adressage non permisrÃ©adressage non applicablerÃ©adressage hors limitedÃ©bordement de rÃ©adressagele rÃ©adressage n'est valide que dans du code thumb1compteur de rÃ©pÃ©tition < 0; .fill ignorÃ©le compteur de rÃ©pÃ©tition ne peut Ãªtre utilisÃ© avec %sinstruction de rÃ©pÃ©tition utilisÃ©e avec une instruction en mode non-registrele dÃ©placement exigÃ© n'a pas Ã©tÃ© donnÃ© dans la rÃ©fÃ©rence indirectebits infÃ©rieurs rÃ©siduels dans le rÃ©adressage diffÃ©rentiel pmemconflit de ressource (A%d)conflit de ressource (fanion C)conflit de ressource (fanion F)conflit de ressource (PSW)conflit de ressource (R%d)reste de la ligne ignorÃ©e; premier caractÃ¨re ignorÃ© est Â«Â %cÂ Â»restauration sans sauvegardeobtenu de mips_ip(%s) insn_opcode = 0x%x opÃ©rande de droite est un grand nombre; entier 0 assumÃ©opÃ©rande de droite est un nombre flottant; entier 0 assumÃ©ror #imm n'est pas supportÃ©erotation ne peut Ãªtre que 0, 8, 16 ou 24arrondi vers le bas le premier opÃ©rande flottant vers un entier signÃ©arrondi vers le bas le premier opÃ©rande flottant vers un entier non signÃ©rva sans symbolesuffixe s dans une instruction de comparaison est dÃ©prÃ©ciÃ©dÃ©bordement du dÃ©calage du code s3_PIC (max 16 bits signÃ©s)mÃªme type de prÃ©fixe utilisÃ© deux foisl'indexe scalaire doit Ãªtre constantindex scalaire hors limitele scalaire doit avoir un indexescalaire hors limitescalaire hors limite pour une instruction de multiplicationfacteur d'Ã©chelle invalide pour cette architecture; a besoin de cpu32 ou 68020 ou plusfacteur d'Ã©chelle de %d sans registre d'indexinstruction score3d.rÃ©adressage sdaoff() utilisÃ© sur une instruction qui ne le supporte pasdeuxiÃ¨meseconde directive .ent trouvÃ©e avant la directive .endsecond opÃ©rande manquantsecond opÃ©rande doit Ãªtre un 1second opÃ©rande de .insn n'est pas constante le second registre devrait Ãªtre plus grand que le premier registrele second registre devrait suivre le tiret dans la liste de registressection %s renommÃ©e plusieurs foisla section Â«Â %sÂ Â» s'est terminÃ©e avec un bloc IT ouvert.section Â«Â %sÂ Â» ayant l'alias Â«Â %sÂ Â» n'est pas utilisÃ©ealignement de section doit Ãªtre >= 4 octets pour garantir la sÃ©curitÃ© de MULS/MULUchangement de section Ã partir de la paire BSPEC/ESPEC n'est pas supportÃ©symboles de section sont dÃ©jÃ globauxrecherche jusqu'Ã la fin de .incbin a Ã©chouÃ© Â«Â %sÂ Â»Ã©crasement de segment sur Â«Â %sÂ Â» est inefficacele FPU choisi ne supporte pas l'instructionl'architecture sÃ©lectionnÃ©e ne supporte pas les instructions de branchements conditionnels largesle processeur sÃ©lectionnÃ© n'a pas toutes les fonctionnalitÃ©s de l'architecture sÃ©lectionnÃ©ele processeur sÃ©lectionnÃ© ne supporte pas la forme Â«Â AÂ Â» de cette instructionle processeur sÃ©lectionnÃ© ne supporte pas la variante 32 bits de l'instruction Â«Â %sÂ Â»le processeur choisi ne supporte pas les opcodes ARMle processeur choisi ne supporte pas l'extension DSPle processeur choisi ne supporte pas le nom de champ PSTATE Â«Â %sÂ Â»le processeur choisi ne supporte pas l'instruction SETPANle processeur choisi ne supporte pas les opcodes THUMBle processeur choisi ne supporte pas Â«Â %sÂ Â»le processeur choisi ne supporte pas Â«Â %sÂ Â» en mode ARMle processeur choisi ne supporte pas Â«Â %sÂ Â» en mode Thumble processeur choisi ne supporte pas Â«Â %sÂ Â» en mode Thumb-2le processeur sÃ©lectionnÃ© ne supporte pas l'instruction fp16le processeur sÃ©lectionnÃ© ne supporte pas le registre spÃ©cialisÃ© demandÃ©le processeur choisi ne supporte pas le nom de registre systÃ¨me Â«Â %sÂ Â»format de cible sÃ©lectionnÃ© Â«Â %sÂ Â» inconnunumÃ©ro de sÃ©quence utilisÃ© pour !tlsgd!%ldnumÃ©ro de sÃ©quence utilisÃ© dans !tlsldm!%ldsÃ©quentielset peut uniquement utiliser le port RD comme sourceset: nombre n'est pas dans les bornes -2147483648..4294967295set: nombre n'est pas dans les bornes 0..4294967295l'utilisation de setend est dÃ©prÃ©ciÃ© avec ARMv8setsw: nombre n'est pas dans les bornes -2147483648..4294967295initialisation incorrecte des attributs de section de %sinitialisation incorrecte du type de section pour %ssetx: registre temporaire G0 illÃ©galsetx: registre temporaire identique au registre de destinationla longueur du dÃ©calage n'est pas entre 0 et 63dÃ©calage par registre pas permis en mode thumbnombre de dÃ©calagesexpression de dÃ©calage attendul'expression de dÃ©calage est trop grandele dÃ©calage doit Ãªtre constantdÃ©calage pas permis pour un champ de bits immÃ©diatopÃ©rateur de dÃ©calage attendudÃ©calage hors limitevaleur de dÃ©calage supÃ©rieure Ã 3 pas permise en mode thumbles dÃ©calages dans les instructions CMP/MOV sont uniquement supportÃ©es dans la syntaxe unifiÃ©ebranchement short avec un dÃ©calage zÃ©ro: utiliser :windicateur de raccourci invalidedevrait avoir 1 ou 2 opÃ©randesdevrait avoir deux opÃ©randesdÃ©bordement de .word signÃ©; commutation peut Ãªtre trop grande; %ld Ã 0x%lxvaleur signÃ©e hors limiteles instructions simd opÃ¨rent sur des valeurs par paires (prÃ©fixe L)l'instruction simple occupe %u octets mais la limite de .bundle_align_mode est %u octetstaille (%ld) hors limite, ignorÃ©taille n'est pas 4 ou 6taille nÃ©gative; .fill ignorÃ©taille de Â«Â %sÂ Â» est dÃ©jÃ %ld; n'a pas Ã©tÃ© changÃ© en %ldla valeur de taille pour la directive d'espace est trop grande: %lxescamotage (%ld) ou compte (%ld) invalide pour la taille du fichier (%ld)escamotage des prÃ©fixes sur cette instructionescamotage d'une instruction de 2 motsla pseudo instruction smi ne devrait pas utiliser une Ã©tiquette dans le champ immquelques symboles sont non dÃ©finis; zÃ©ro assumÃ©sourceles unitÃ©s source et adresse ne doivent pas Ãªtre partagÃ©es pour ce mode d'adressageles incrÃ©ments source et destination doivent correspondresource et destination doivent Ãªtre diffÃ©rentsregistres source et destination doivent Ãªtre dans des unitÃ©s diffÃ©rentesopÃ©rande source doit Ãªtre une adresse absolue de 16 bitsopÃ©rande source doit Ãªtre un registre de 8 bitsregistre source doit Ãªtre dans l'unitÃ© de dÃ©clenchementregistre source doit Ãªtre r1registre source identique Ã la base de rÃ©Ã©criture arriÃ¨rele registre source devrait avoir un numÃ©ro pairles registres source devraient avoir un numÃ©ro pairsource1 et dest doivent Ãªtre le mÃªme registreallocation d'espace trop complexe dans la section absolueallocation d'espace trop complexe dans la section communesparc convert_frag instruction spÃ©ciale de gauche Â«Â %sÂ Â» Ã©crase l'instruction Â«Â %sÂ Â» du conteneur de droiteposition spÃ©cifiÃ©e n'Ã©tait pas alignÃ©e TETRAenregistrement spill_mask non implÃ©mentÃ©.spu convert_frag opÃ©randes parasites; (%d opÃ©randes/instructions au maximum)l'instruction st/ld offset 23 a Ã©tÃ© dÃ©sactivÃ©e.la disposition de la trame de pile ne correspond pas Ã la routine de personnalitÃ©disposition de la trame de pile trop complexe pour le dÃ©rouleurincrÃ©ment de pile doit Ãªtre un multiple de 4le dÃ©calage du pointeur de pile est trop grand pour la routine de personnalitÃ©prÃ©fixe Â«Â %sÂ Â» autonomeadresse de dÃ©part non supportÃ©eÃ©trange hauteur de papier, initialisÃ© sans formatÂ«Â \Â Â» superflule pas doit Ãªtre un multiple de 64, les 6 bits infÃ©rieurs sont ignorÃ©spas de 2 pas disponible quand la taille de l'Ã©lÃ©ment est 8chaÃ®ne trop grande (%lu octets)chaÃ®nes doivent Ãªtre placÃ©es dans une sectionsupporter l'interaction ARM/Thumbswp{b} est dÃ©prÃ©ciÃ© pour ARMv6 et ARMv7swp{b} est obsolÃ¨te pour ARMv8 et suivantssymbole Â«Â %sÂ Â» est indÃ©fini; zÃ©ro assumÃ©le symbole %s est dans une section diffÃ©rentele symbole %s est faible et pourrait Ãªtre remplacÃ© plus tardsymbole Â«Â %sÂ Â» dÃ©jÃ dÃ©finisymbole Â«Â %sÂ Â» ayant l'alias Â«Â %sÂ Â» n'est pas utilisÃ©symbole Â«Â %sÂ Â» dÃ©jÃ dÃ©finisymbole Â«Â %sÂ Â» ne peut Ãªtre Ã la fois weak et commonsymbole Â«Â %sÂ Â» est dÃ©jÃ dÃ©finisymbole Â«Â %sÂ Â» est dÃ©jÃ dÃ©fini comme Â«Â %sÂ Â»/%s%ldboucle de dÃ©finition de symbole rencontrÃ©e Ã Â«Â %sÂ Â»symbole dans .toc ne concorde avec aucun .tcnom de symbole pas reconnu dans la locale actuelledÃ©bordement lors du calcul de la taille du symbolesymbole trop Ã©loignÃ©type de symbole Â«Â %sÂ Â» n'est supportÃ© que par les cibles GNU et FreeBSDtype de symbole Â«Â %sÂ Â» n'est supportÃ© que par les cibles GNUsymbole%dsymbole+offset non supportÃ© dans le got tlsopÃ©rande symbolique pas permissymboles assignÃ©s avec .asg doivent dÃ©buter avec une lettresymboles assignÃ©s avec .eval doivent dÃ©buter avec une lettreerreur de syntaxeerreur de syntaxe dans .startof. ou .sizeof.erreur de syntaxe dans @(disp,[Rn, gbr, pc])erreur de syntaxe dans @(r0,...)erreur de syntaxe dans @(r0...)erreur de syntaxe dans la directive de contrÃ´le structurÃ©eerreur de syntaxe: code de condition inattenduerreur de syntaxe: attendu Â«Â ]Â Â», obtenu Â«Â %cÂ Â»erreur de syntaxe: spÃ©cificateur de table d'entrÃ©es Â«Â %sÂ Â» invalideerreur de syntaxe: registre inattenduerreur de syntaxe: registre systÃ¨me inattenduerreur de syntaxe: valeur manquante avant le nom du registreerreur de syntaxe: registre vectoriel inattenduerreur de syntaxes; Â«Â )Â Â» n'est pas permis icierreur de syntaxe; fin de ligne, attendait Â«Â %cÂ Â»erreur de syntaxe: Â«Â ,Â Â» attendueerreur de syntaxe; obtenu Â«Â %cÂ Â», attendait Â«Â %cÂ Â»erreur de syntaxe; Â«Â (Â Â» manquante aprÃ¨s le dÃ©placementerreur de syntaxe: Â«Â )Â Â» manquante aprÃ¨s le registre de basele nom de registre systÃ¨me Â«Â %sÂ Â» est dÃ©prÃ©ciÃ© et pourrait Ãªtre supprimÃ© dans une version ultÃ©rieureregistres systÃ¨mes ne peuvent Ãªtre inclus dans la listeÃ©tiquette non repÃ©rÃ©e pour le .tag %scible de l'instruction %s doit Ãªtre une Ã©tiquettecible hors limiterÃ©adressage tdaoff() utilisÃ© sur une instruction qui ne le supporte pascommutateur temporaire pour la vidangetexte de l'Ã©tiquette Â«Â %sÂ Â» alignÃ© sur une frontiÃ¨re impairel'architecture %d bits %s ne supporte pas l'extension Â«Â %sÂ Â»le nom %s Â«Â %sÂ Â» est trop long (maximum 16 caractÃ¨res)le format de fichier XCOFF ne supporte pas des sections arbitrairesl'extension Â«Â %sÂ Â» requiert %s%d Ã la rÃ©vision %d ou plusl'extension Â«Â %sÂ Â» requiert des FPR 64 bitsl'extension Â«Â %sÂ Â» a Ã©tÃ© retirÃ©e dans %s%d rÃ©vision %dle nombre de .indirect_symbols dÃ©finis dans la section %s ne correspond pas au nombre attendu (%d dÃ©finis, %d attendus)l'offset 0x%08lX n'est pas reprÃ©sentableles seuls suffixes valides ici sont Â«Â (plt)Â Â» et Â«Â (tlscall)Â Â»l'offset immÃ©diat facultatif ne peut Ãªtre que zÃ©role deuxiÃ¨me registre source Â«Â %s%sÂ Â» dÃ©note implicitement Â«Â %s%.3s%dÂ Â» vers le groupe source Â«Â %s%.3s%dÂ Â» dans Â«Â %sÂ Â»le registre source ne doit pas Ãªtre $0le registre source ne doit pas Ãªtre $31l'option spÃ©cifiÃ©e n'est pas acceptÃ©e pour PSBl'option spÃ©cifiÃ©e n'est pas acceptÃ©e dans ISBle type de rÃ©adressage spÃ©cifiÃ© n'est pas permis avec un registre 32 bitsle type de rÃ©adressage spÃ©cifiÃ© n'est pas permis pour MOVKla moitiÃ© supÃ©rieure d'un registre FP/SIMD 128 bits est attenduele type de %s est trop complexe; il sera simplifiÃ©l'utilisation de -mvle requiert -a32.l'utilisation de -mvle requiert un grand boutiste.L'instruction pour passer la main %s peut ne pas Ãªtre dans la plage de dÃ©lai.il n'y a pas de tailles de rÃ©adressages relatifs au PCil n'y a pas de rÃ©adressage non signÃ© relative au PCtroisiÃ¨meCe DS n'est pas encore supportÃ©ece mode d'adressage n'est pas applicable pour l'opÃ©rande de destinationce mode d'adressage requiert une rÃ©Ã©criture du registre de basece rÃ©adressage de groupe n'est pas permis sur cette instructioncette instruction n'accepte pas un accumulateurcette instruction n'accepte pas un immÃ©diatcette instruction ne supporte pas l'indexagecette instruction implique l'utilisation de AdvSIMD du ARMv8.1.cette instruction requiert un adresse post indexÃ©ecette instruction ne va pas rÃ©Ã©crire le registre de basecette instruction va rÃ©Ã©crire le registre de basece modificateur de rÃ©adressage n'est pas permis sur cette instructioncette chaÃ®ne ne peut pas contenir Â«Â \0Â Â»ce type de registre ne peut pas Ãªtre indexÃ©l'instruction conditionnelle thumb devrait Ãªtre dans le bloc ITtrop peu d'opÃ©randestrop de !literal!%ld pour %strop d'entrÃ©es .dimtrop d'entrÃ©es .sizetrop de registres GREG allouÃ©s (maximum %d)trop d'instructions IVC2 Ã empaqueter ensemblestrop d'instructions IVC2 Ã empaqueter avec une instruction core 16 bitstrop d'instructions IVC2 Ã empaqueter avec une instruction core 32 bitstrop d'argumentstrop de correctifstrop d'instructions dans le paquet d'exÃ©cutiontrop de lda insns pour !gpdisp!%ldtrop de ldah insns pour !gpdisp!%ldtrop de lituse insns pour !lituse_tlsgd!%ldtrop de lituse insns pour !lituse_tlsldm!%ldtrop de rÃ©fÃ©rences mÃ©moires pour Â«Â %sÂ Â»trop d'opÃ©randestrop d'opÃ©randes (%d) pour Â«Â %sÂ Â»; attendu %dtrop d'opÃ©randes dans l'instructiontrop d'opÃ©randes Ã Â«Â %.*sÂ Â»trop d'arguments positionnelstrop de registres dans la liste des registres vectorielstrop de Â«Â st_EndÂ Â»trop d'opcodes unwindtrop d'opcodes unwind pour la routine de personnalitÃ© 0trop d'instructions unwindrebut aprÃ¨s l'expression: %straduction de bgeni en movitraduction de bmaski en movitraduction de mgeni en movitraduction en Â«Â %s %s%sÂ Â»traduction en Â«Â %s %s%s,%s%sÂ Â»traduction en Â«Â %spÂ Â»exception par trappe non supportÃ©e sur ISA 1tentative d'initialisation d'un symbole non reconnuÂ : %s fichier Â«Â %sÂ Â» tronquÃ©, %ld de %ld octets lusdeux pseudo-op .function sans .ef intermÃ©diairetype de rÃ©adressage %d fait ? mauvaise concordance de type dans la liste des registres vectorielsle spÃ©cificateur de type a le mauvais nombre de partiestypes spÃ©cifiÃ©s Ã la fois dans la mnÃ©monique et les opÃ©randesincapable de calculer les instructions ADRL pour le dÃ©calage PC de 0x%lximpossible de continuer cette assemblage.impossible de produire l'opcode unwind pour le dÃ©calage du pointeur de trameimpossible de produire l'opcode unwind pour le registre du pointeur de trame %dimpossible de produire l'opcode unwind pour le registre %dimpossible de repÃ©rer l'emplacement du fichier Ã inclure: %simpossible d'empaqueter %s de lui-mÃªme ?impossible de rÃ©introduire le fichier dans le tamponÂ : %s impossible de rÃ©pÃ©ter insn %simpossible de rÃ©tablir l'adresse de retour Ã partir du registre prÃ©cÃ©demment rÃ©tabliincapable d'Ã©largir l'instructioncible de branchement non alignÃ©e: %d octets Ã 0x%lxdonnÃ©es non alignÃ©es sur une position absolue ne sont pas supportÃ©esinstruction d'entrÃ©e pas alignÃ©eboucle non alignÃ©e: %d octets Ã 0x%lxregistre non alignÃ©numÃ©ro de fichier %ld non assignÃ©crochets non pairÃ©s dans l'opÃ©rande %d.parenthÃ¨ses non pairÃ©es dans l'opÃ©rande %d.Â«Â (Â Â» non fermÃ©ecorrectif indÃ©codableinstruction indÃ©codable dans le fragment d'instructioncombinaison d'opÃ©randes indÃ©finielabel local Â«Â %sÂ Â» non dÃ©finisymbole Â«Â %sÂ Â» indÃ©fini dans le rÃ©adressage PCRsymbole non dÃ©fini %s utilisÃ© comme valeur immÃ©diatesymbole indÃ©fini pour l'opcode Â«Â %sÂ Â»correctif %s inattendudirective .cantunwind inattendue.cfi_inline_lsda inattendudirective .handlerdata inattenduedirective .unwind_movsp inattenduetype de rÃ©adressage 12-bits inattendutype de rÃ©adressage 18-bits inattenduexpression relative au PC inattenduerÃ©adressage TLS inattenduÂ«Â "Â Â» inattendue dans l'expressionmode d'adressage inattendu pour %sbit inattendu aprÃ¨s APSRcaractÃ¨re Â«Â %cÂ Â» inattendu dans la taille d'Ã©lÃ©mentcaractÃ¨re Â«Â %cÂ Â» inattendu dans le prÃ©dicat de typecaractÃ¨re Â«Â %cÂ Â» inattendu dans le spÃ©cificateur de typecaractÃ¨res inattendus aprÃ¨s l'instructionvirgule inattendue aprÃ¨s le nom de mnÃ©monique Â«Â %sÂ Â» â€” Â«Â %sÂ Â»virgule inattendue avant l'opÃ©rande facultatif omisfin inattendue du fichier dans irp ou irpcfin inattendue du fichier dans la dÃ©finition de macro Â«Â %sÂ Â»fin de ligne inattenduecorrectif inattenduconstante nÃ©gative inattendueregistre inattendu dans l'opÃ©rande immÃ©diatinformations de taille de section inattenduesopÃ©rateur de dÃ©calage inattenduclasse de stockage inattendue %d%d non traitÃ© instruction CFA non gÃ©rÃ©e pour le unwind (%d)correctif de rÃ©adressage local %s non traitÃ©code d'opÃ©rande %d non gÃ©rÃ©rÃ©adressage %s non traitÃ© dans md_pcrel_from_sectiontype de rÃ©adressage non traitÃ© %snon traitÃ©: .proc %s,%dopcode non implÃ©mentÃ© Â«Â %sÂ Â»suffixe de rÃ©adressage non implÃ©mentÃ©segment %s non implÃ©mentÃ© dans l'opÃ©randemodificateur d'expression toc32 non implÃ©mentÃ©modificateur d'expression toc64 non implÃ©mentÃ©expression dÃ©sindexÃ©e utilisÃ©e dans une instruction de prÃ©chargementinconnuargument de -mpid= inconnu Â«Â %sÂ Â»valeur de .gnu_attribute inconnuesous directive .loc inconnue Â«Â %sÂ Â»version EABI inconnue Â«Â %sÂ Â» DSP inconnu Â«Â %sÂ Â»caractÃ¨re %c inconnu pour le prÃ©fixe DSP %sEABI inconnue Â«Â %sÂ Â» configuration FPU inconnue Â«Â %sÂ Â» niveau ISA inconnu %sISA ou architecture inconnue %sMCU inconnue: %s abi Â«Â %sÂ Â» inconnue mode d'adressage inconnu %snom d'architecture inconnu Â«Â %sÂ Â» extension d'architecture inconnue Â«Â %sÂ Â»architecture inconnuearchitecture inconnue %sarchitecture inconnue Â«Â %sÂ Â»architecture inconnue Â«Â %sÂ Â» extension d'architecture inconnue Â«Â %sÂ Â» architecture inconnue: %s argument inconnu pour .usepvligne de base inconnue Â«Â %sÂ Â» code de condition inconnue: %scontrainte inconnue Â«Â %cÂ Â»cpu inconnu Â«Â %sÂ Â»CPU par dÃ©faut inconnu = %s, systÃ¨me d'exploitation = %sdirective inconnueÃ©chappement inconnu Â«Â \%cÂ Â» dans la chaÃ®ne; ignorÃ©type d'exÃ©cution inconnue passÃ© Ã write_2_short()expression inconnue dans l'opÃ©rande %sexpression inconnue dans l'opÃ©rande %s. Utiliser #llo() #lhi() #hlo() #hhi() taille de correctif inconnueABI virgule flottante inconnue Â«Â %sÂ Â» format de virgule flottante inconnu Â«Â %sÂ Â» mnÃ©monique virgule flottante inconnueÂ : Â«Â %sÂ Â»caractÃ¨re inconnu pour le prÃ©fixe virgule flottantetype de virgule flottante inconnu Â«Â %cÂ Â»fpu inconnu Â«Â %sÂ Â»rÃ©adressage de groupe inconnumode IT implicite Â«Â %sÂ Â» inconnu, devrait Ãªtre arm, thumb, always ou never.instruction inconnue Â«Â %sÂ Â»interruption %s inconnuemnÃ©monique inconnue Â«Â %sÂ Â» â€” Â«Â %sÂ Â»mnÃ©monique inconnueÂ : Â«Â %sÂ Â»opcode inconnuopcode inconnu Â«Â %sÂ Â»opcode inconnu %sopcode inconnu Â«Â %sÂ Â»opcode inconnu Â«Â %sÂ Â»opcode ou nom de format inconnu Â«Â %sÂ Â»opcode inconnu: %sopcode inconnu Â«Â %sÂ Â»opÃ©rande inconnu %sdÃ©compte d'opÃ©rande inconnuopÃ©rande de dÃ©calage inconnue: %x opÃ©rande inconnu pour .archopÃ©rateur %s inconnu. Voulez-vous dire X(Rn) ou #[hl][hl][oi](CONST) ?attribut de section Â«Â %sÂ Â» inconnu ou invalidetype de section Â«Â %sÂ Â» inconnu ou invalidenom de champ PSTATE inconnu ou manquantnom d'opÃ©ration inconnu ou manquantoption inconnue ou manquante pour PSBnom de registre systÃ¨me inconnu ou invalideparamÃ¨tre inconnu aprÃ¨s la directive .SECTION: %stype de procÃ©dure inconnuefanion de profilage inconnu est ignorÃ©.pseudo-op inconnu: Â«Â %sÂ Â»type d'enregistrement %d inconnu (dans %s)registre %s inconnuregistre Â«Â %sÂ Â» inconnu -- .req ignorÃ©registre Â«Â %sÂ Â» inconnualias de registre Â«Â %sÂ Â» inconnurÃ©adressage inconnu (%u)modificateur de rÃ©adressage inconnuattribut de section inconnu %sattribut de section inconnu Â«Â %cÂ Â»function dÃ©finie par l'utilisateur %s inconnueopÃ©ration vectorielle inconnueÂ : Â«Â %sÂ Â»spÃ©cificateur de largeur inconnu Â«Â .%cÂ Â»opÃ©rande inconnu/incorrectÂ«Â [Â Â» non pairÃ©directive .end non pairÃ©ecouple DCTI imprÃ©visiblechargement imprÃ©visible d'une paire de registres â€” Â«Â %sÂ Â»transfert imprÃ©visible avec rÃ©Ã©criture â€” Â«Â %sÂ Â»type de CPU RX %s non reconnuÂ»valeur d'alignement non reconnue dans la directive .SECTION: %sargument non reconnu Ã l'option -mcpu Â«Â %sÂ Â»type de cpu non reconnu Â«Â %sÂ Â»instruction %s non reconnuemodificateur de taille d'instruction .%c non reconnuversion sur %d bits inconnue de l'opcode microMIPStype .linkonce non reconnu Â«Â %sÂ Â»attribut de .section non reconnu: a,e,w,x,M,S,G,T ou un nombre attendufanion CPS non reconnucaractÃ¨res non reconnus Ã la fin du traitement parallÃ¨le insnCPU par dÃ©faut non reconnu Â«Â %sÂ Â»nom de l'Ã©mulation non reconnu Â«Â %sÂ Â»version Ã©tendue d'opcode MIPS16 non reconnuefanion non reconnuoption fopt non reconnueopcode non reconnuopcode non reconnuÂ : Â«Â %sÂ Â»option Â«Â %sÂ Â» non reconnueoption non reconnue -%c%spseudo instruction %s non reconnuenom de registre non reconnu Â«Â %sÂ Â»type de rÃ©adressage non reconnusuffixe de rÃ©adressage non reconnuattribut de section non reconnucommande de section n'est pas reconnue Â«Â %sÂ Â»type de section non reconnutype de section non reconnu Â«Â %sÂ Â»type de stab non reconnu Â«Â %cÂ Â»suffixe de symbole non reconnutype de symbole non reconnu Â«Â %sÂ Â»mode de syntaxe Â«Â %sÂ Â» non reconnuversion non Ã©tendue d'opcode MIPS16 non reconnuecompteur de rÃ©pÃ©tition ne peut Ãªtre rÃ©solu ou est non positif; utilise 1expression non rÃ©solue qui doit Ãªtre rÃ©soluene peut rÃ©soudre le symbole cible de boucle: %sregistre non dÃ©calÃ© requisvaleur non signÃ©e hors limitetaille de rÃ©adressage BFD %d non supportÃ©etaille de rÃ©adressage BFD non supportÃ©e %utype de DC non supportÃ©alignement non supportÃ©alignement non supportÃ© pour l'instructiondiffusion non supportÃ©valeur d'octet non supportÃ©e; utiliser un suffixe diffÃ©rentconstante non supportÃ©e dans un rÃ©adressagetaille de constante %d non supportÃ©e taille du correctif %d non supportÃ©efanion %i non supportÃ© dans la directive de lignecorrectif fptr non supportÃ©taille du correctif fptr %d non supportÃ©einstruction Â«Â %sÂ Â» non supportÃ©econstante de grande taille non supportÃ©emasquage non supportÃ©einformation de section mbind non supportÃ©e: %srÃ©adressage non supportÃ©rÃ©adressage non supportÃ© vers %stype de rÃ©adressage non supportÃ© pour un dÃ©calage de champ DStype de rÃ©adressage non supportÃ©attribut de section non supportÃ© Â«Â %cÂ Â»attribut de section non supportÃ© â€” Â«Â aÂ Â»arrondi/sae statique non supportÃ©symbole de soustraction non supportÃ©syntaxe non supportÃ©eutilisation non supportÃ© de %sutilisation non supportÃ© de .ehwordutilisation non supportÃ©e de .gpdwordutilisation non supportÃ© de .gpwordtaille de variable ou valeur de remplissage non supportÃ©eregistre d'index vectoriel non supportÃ©non supportÃ© avec les mnÃ©moniques IntelchaÃ®ne non terminÃ©echaÃ®ne non terminÃ©e; saut de ligne insÃ©rÃ©Â«Â untilÂ Â» sans Â«Â repeatÂ Â»opcode unwind trop longla trame dÃ©roulÃ©e a une taille nÃ©gativepointeur de pile dÃ©roulÃ© n'est pas alignÃ© sur un mot doubleutiliser -march=armv2utiliser -march=armv2autiliser -march=armv3utiliser -march=armv3mutiliser -march=armv4utiliser -march=armv4tutiliser -march=armv5utiliser -march=armv5tutiliser -march=armv5teutiliser -mcpu=allutiliser -mcpu=arm1utiliser -mcpu=arm2utiliser -mcpu=arm250utiliser -mcpu=arm3utiliser -mcpu=arm6utiliser -mcpu=arm600utiliser -mcpu=arm610utiliser -mcpu=arm620utiliser -mcpu=arm7utiliser -mcpu=arm70utiliser -mcpu=arm700utiliser -mcpu=arm700iutiliser -mcpu=arm710utiliser -mcpu=arm7100utiliser -mcpu=arm710cutiliser -mcpu=arm710tutiliser -mcpu=arm720utiliser -mcpu=arm720tutiliser -mcpu=arm740tutiliser -mcpu=arm7500utiliser -mcpu=arm7500feutiliser -mcpu=arm7dutiliser -mcpu=arm7diutiliser -mcpu=arm7dmutiliser -mcpu=arm7dmiutiliser -mcpu=arm7mutiliser -mcpu=arm7tdmiutiliser -mcpu=arm8utiliser -mcpu=arm810utiliser -mcpu=arm9utiliser -mcpu=arm920utiliser -mcpu=arm940utiliser -mcpu=arm9tdmiutiliser -mcpu=iwmmxtutiliser -mcpu=strongarmutiliser -mcpu=strongarm110utiliser -mcpu=strongarm1100utiliser -mcpu=strongarm1110utiliser -mcpu=xscaleutiliser -mfpu=fpa10utiliser -mfpu=fpa11utiliser -mfpu=fpeutilisez .code16 pour assurer un mode d'adressage correctutiliser soit -mfpu=softfpa ou -mfpu=softvfputiliser le pointeur de tramel'utilisation de .indirect_symbols requiert Â«Â -dynamicÂ Â»l'utilisation de PC dans cette instruction est dÃ©prÃ©ciÃ©eutilise des vieux et nouveaux styles d'options pour dÃ©finir le type de CPUutilise des vieux et nouveaux styles d'options pour dÃ©finir le type de FPUutilisation de r13 est obsolÃ¨teutilisation de r15 dans le blx en mode ARM n'est pas trÃ¨s utileutilisation de r15 dans le bx en mode ARM n'est pas trÃ¨s utileutilisation de r15 dans le bxj n'est pas trÃ¨s utileutiliser la vÃ©rification de la taille de la pilea utilisÃ© $%u avec Â«Â .set at=$%uÂ Â»a utilisÃ© $at sans Â«Â .set noatÂ Â»utilise utilise Â«Â %s%sÂ Â» au lieu de Â«Â %s%sÂ» en raison du suffixe Â«Â %cÂ Â»utilise un champ de bits dont la largeur est zÃ©rospÃ©cificateurs petit/gros boutistes possibles sont be ou levaleur %d est hors limite. Utiliser #lo() ou #hi()valeur %ld hors limitevaleur 0x%I64x tronquÃ©e Ã 0x%I64xvaleur 0x%llx tronquÃ©e Ã 0x%llxvaleur 0x%lx tronquÃ©e Ã 0x%lxvaleur 0x%x hors de la limite Ã©tendue.valeur pas dans la gamme [-0xffffffff, 0xffffffff]valeur pas dans la gamme [0, 0x7fffffff]valeur pas dans la gamme [0, 0xffffffff]valeur de %ld hors de l'Ã©tendue de dÃ©calage sur un octet.valeur de %ld hors de l'Ã©tendue de dÃ©calage sur un double mot.valeur de %ld hors de l'Ã©tendue de dÃ©calage sur un mot.Valeur de %ld trop grande pour un branchement de 16 bitsValeur de %ld trop grande pour un branchement de 8 bitsla valeur de %s est trop grande pour le champ de %d octet Ã %sla valeur de %s est trop grande pour le champ de %d octets Ã %svaleur hors limitevaleur hors limite: 0x%xvaleur stockÃ©e pour r%d est INCONNUEvaleur trop grande pour un champ de 1 octetvaleur trop grande pour un champ de 2 octetsvaleur trop grande pour entrer dans %d bitsl'Ã©lÃ©ment d'un vecteur doit Ãªtre une constanteregistre vectoriel attendutype vectoriel attenduvfmal/vfmsl avec le type FP16 ne peut pas Ãªtre conditionnel, le comportement est IMPRÃ‰VISIBLEle numÃ©ro de vue ne concorde pasmÃ©moire virtuelle Ã©puisÃ©ele groupe vliw doit avoir une instruction core et une instruction copro.avertir Ã propos des symboles qui correspondent Ã des noms d'instructions [dÃ©faut]avertissement: symbole %s n'a pas de csectOptions en assembleur wasm32: les suffixes de largeurs sont invalides en mode ARMles suffixes de largeur sont invalides en mode ARM -- Â«Â %sÂ Â»mot de NOP ajoutÃ© entre Â«Â word multiplyÂ Â» et Â«Â 16- bits multiplyÂ Â»mot de NOP ajoutÃ© entre Â«Â word multiplyÂ Â» et Â«Â loadÂ Â»rÃ©Ã©criture (!) doit Ãªtre utilisÃ©e pour VLDMDB et VSTMDBrÃ©Ã©criture arriÃ¨re du registre de base est IMPRÃ‰VISIBLErÃ©Ã©criture du registre de base en Ã©tant dans une liste de registres est IMPRÃ‰VISBLErÃ©Ã©criture utilisÃ©e dans une instruction de prÃ©chargementla valeur de rÃ©Ã©criture doit Ãªtre une constante immÃ©diatel'Ã©criture ou la modification # est imprÃ©visibleÃ©crire dans APSR sans spÃ©cifier de bitmask est rÃ©prouvÃ©argument erronÃ© pour .cfi_personality_idnombre d'opÃ©randes erronÃ©mauvais nombre d'opÃ©randes pour Â«Â %sÂ Â»mauvais registre dans la liste des registres en virgule flottantesecond argument erronÃ© dans .cfi_lsdasecond argument erronÃ© dans .cfi_personalityinstruction de mauvaise taille dans un slot d'un branchement de %u bits diffÃ©rÃ©troisiÃ¨me argument erronÃ© dans .cfi_val_encoded_addrÃ©chec xtensa-isa: %svous ne pouvez pas utiliser Â«Â pop %scsÂ Â»vous ne pouvez spÃ©cifier qu'un type uniquevous devez utiliser une directive hi/lo ou une macro 16 bits pour charger une valeur 16 bit.rÃ©adressage zdaoff() utilisÃ© sur une instruction qui ne le supporte paszÃ©ro assumÃ© pour l'expression manquantele fanion zÃ©ro n'est pas valide pour cette instructionzÃ©ro utilisÃ© comme valeur immÃ©diatele masquage par zÃ©ro est uniquement autorisÃ© avec un masque en Ã©criture{entrÃ©e standard}