WMFW(7�$C�nh�,Wed 09 Jul 2025 15:57:07 GMT Daylight Time��d'� � ��(� 5 �>�  .f �& � �F �fHZ$�8 ~ � �9 Y~� � � � |8� � � � �0� 0 � �+� M � � d��  j(  � � 4�  " � ;�! ) Wb � ��$ B� �&�R�( � �"b�) � �#V �* ' � B��3 �� �4 ��1 ? �0T0�5 O �7�J�/ 27��ޭ�U  �4 ���ROw!O����@�=aO�=����@P�@ � P �� ��H4��HD� �� a���!К@�� @ �� � �Ö™!�H�H���u�t�@t�@��H� H�a�@���@Õš@��H�@��g��z��ՙ�RSR��mÙ™P��l_q{��q����!� P!O�n���@@ ��@�� �O ������@�@�#0�Y@P��Z�"�Fns�����@z�����@ ������AO�}����@ �� �� �������@b���� ��Of� ���� ���!�YQO���)� n���!�@�� I��A�D@# i� @�Ȅ�@�{��G���@�,��D����{���Ȝ�@�m�Ù�� �@��X�Ú��c�� AO� Ȅ�@Ò™�@O�{��@�������{��G���@���)� � �� �����D)��� � ����O��������a���,����a��)1��@ @^ny� ��p�����P�O�~�� �@-�n����ɚ ���=��_� )p Q�QO�O`�_���a��_;B U�������� �ʙ �f����O���@��)���%2 �)��9�I�������k�O���A ����!� ���� �ᱱ� ��!�@O !������@� 1�n���O��_�f���/���^ �u�r ) ��_Q�� _4)�1�i�i�O��_A.nb�a��_�RQ_8 �I��� � �����P�������%�@n�@��@�$���mf� 0��� �J�aJiV�0���Ah�iVh0���AV�i�Ah0��V�i���h0�@��0P#�0� �H� �p'�F� �Q�0Pm��H��P0%!0�F� ��0p�M��@������_��8��R�@��@�ä�¬ï¿½ï¿½ï¿½�I���O�*�*��Ix���O�I���*�I*�@�������`�����B��@�0F��(���������K���O�����@� ���!�p� @ ������ ����@� �I���*� n Q��� ����� An��  ������!P���� �  O��� �����������P�*��H�����@)� ��'\�,I0 ��O�O�@`� qn�I� ���IÙ��-IxI��0q��@��@m �Oə���@�!O�������p �� p��� ��NJ����@�Б��_�_�1�Q�/3�   P &�`6� ? 0 v�pA_� _����@���@�� ����"�O ����A�@�� `���@ ���  ���! �耠 �@�*�0"A��%l�� !�@� 1O �����@�4�0�� �0 ��� Ù° �$L8�ٰȸ4踆��L�1� !�1ȸFY@LH Ћã�ˆï¿½`�d��a�d���p����� �ꆆñ�Ÿ�� O��m��B������@I@mYT����@ )�%��&�$b���_`�~�i����n�~�a\����l����#�a����ʠ�+s���É��v0�%@ 0��Q�0��� �%��>Ö�@� oѪ�;!����0�@\��֞������ m�#Ñ·�������� eO���9����@�dI�K��!��S �A��@!i (i z��f�%��7�����v+�%0!i (7�f���{�%m��� �l�ёTO�Tx�!a�%e XP �'5����'l�1�U�a� �~�� %Q\S��� oѪ�����v�d�\�֠������ m��" i�������� eO���DP��X%H����|� (��!i�%o�����v�0�@�� (��!i�%o�����@mv�T��@�!aO�e����%��e�  �� @�$n��%H%��(��� I� �I&���� �� �� J �&�� � � ��� II�H�� � %h.����,� ��@�!�Uq�T����@�%� I�(ÞŠ���� �� % ��I��� �� �� % � ������ I� � %����h.��@�.A���h�PC��å���|�@,�F��A�L������l�M�y���N�5�L�်���2 � R��1�������%M�9O��(��Sh�&��������h �r���%���J(m���v��x����(@a���� x�%�m����&(��UH��� ������h�r�(m%����J��@[�v�T@x����( a�%��x��m ��EO�T�0�@ h���FEm�����'Q�d}��A���r%$�9�XaI%k����h �h �(>��\m mn�!D������I�k���� a�%����"���P$�� ������h�r�(m%����J��@[�vT�� d����iaK��� �%�`O ��P ��q�@hm�ҀE��Ȝ��'a�i)�%q����G$�y&��i����]��m����(h�\h m>��!m ��n�DY���r��'���@��(��&�������h �r���%���J(m@[��v��Tñ‘�˜ï¿½�(@xx�x�� �� �Qh ��h�H8C������&������(9h Fr�F�,X��X`m���v�x���(Ie��ÙŽ!�m��8��&�����(�h F��F�9X�rX`m,[���v�@���T(Ix����!em�OኀP�`J��@ �q��hm���@��D�FIRMWARE_CS35L634 FW_HL_STTFIRMWARE_CS35L63_HALO_STATE< FW_HL_HARTBATFIRMWARE_CS35L63_HALO_HEARTBEAT< FW_ADO_BLK_SZFIRMWARE_CS35L63_AUDIO_BLK_SIZE� 8 FW_RFCLK_SRCFIRMWARE_CS35L63_REFCLK_SRC� DFW_PLL_RFCLK_FRQ FIRMWARE_CS35L63_PLL_REFCLK_FREQ� D FW_PLL_F_MCLK%FIRMWARE_CS35L63_REFCLK_PLL_FREQ_MCLK8 FW_BOT_RASNFIRMWARE_CS35L63_BOOT_REASON�@ FW_REFCLK_DET"FIRMWARE_CS35L63_REFCLK_DETECT_32K�<FW_HW_CLCK_STTFIRMWARE_CS35L63_HW_CLOCK_STATE�@FW_CP_MTR_ENBL!FIRMWARE_CS35L63_CPU_METER_ENABLE�DFW_MPS_OVRRN_FLG"FIRMWARE_CS35L63_MIPS_OVERRUN_FLAG�DFW_MIPS_OR_HBN$FIRMWARE_CS35L63_MIPS_OVERRUN_HB_NUM�H FW_DPLL_DB_T*FIRMWARE_CS35L63_DPLL_UNLOCK_DEBOUNCE_TYPE�HFW_DPLL_DB_CNT+FIRMWARE_CS35L63_DPLL_UNLOCK_DEBOUNCE_COUNT�4 FW_TN_TKNFIRMWARE_CS35L63_TUNE_TOKEN�� EVENT_HANDLER�� GPIO�� MAILBOX, QUEUE_BASEMAILBOX_QUEUE_BASE, QUEUE_LENMAILBOX_QUEUE_LEN,QUEUE_WTMAILBOX_QUEUE_WT,QUEUE_RDMAILBOX_QUEUE_RD$STATUSMAILBOX_STATUS�8� PM<PM_TIMEOUT_TICKSPM_PM_TIMER_TIMEOUT_TICKS� , PM_CUR_STATEPM_PM_CUR_STATE4 PM_PWR_ON_SEQPM_POWER_ON_SEQUENCE� �0ACTIVE_SEQUENCEPM_ACTIVE_SEQUENCE���4STANDBY_SEQUENCEPM_STANDBY_SEQUENCE���� AUDIO_SYSTEM4 AS_ADO_STTAUDIO_SYSTEM_AUDIO_STATE�0 AS_LST_CMDAUDIO_SYSTEM_LAST_CMD� D AS_STA_2_SYD&AUDIO_SYSTEM_STRM_ACTIVE_TO_SYNTH_DONE� H AS_SYA_2_STA*AUDIO_SYSTEM_SYNTH_ACTIVE_TO_STREAM_ACTIVE� DAS_PLL_RESYNC_R&AUDIO_SYSTEM_AMP_PLL_UNLOCK_RESYNC_REQ�H AS_STA_2_SYA*AUDIO_SYSTEM_STREAM_ACTIVE_TO_SYNTH_ACTIVE�(AS_ERRRAUDIO_SYSTEM_ERROR�8 AS_PAK_CP_LADAUDIO_SYSTEM_PEAK_CPU_LOAD�<AS_CRRNT_CP_LADAUDIO_SYSTEM_CURRENT_CPU_LOAD�@AS_SYNTHSS_ENBLDAUDIO_SYSTEM_SYNTHESIS_ENABLED�"4 AS_ADO_STTSAUDIO_SYSTEM_AUDIO_STATUS�#0 AS_PRJCT_IDAUDIO_SYSTEM_PROJECT_ID$0 AS_CHNNL_IDAUDIO_SYSTEM_CHANNEL_ID%8 AS_SNPSHT_IDAUDIO_SYSTEM_SNAPSHOT_ID�� MDSYNC�p� ULTRASONIC�P ULTRASONIC_EN3ULTRASONIC_ULTRASONIC_CTRL_STRUCT_ULTRASONIC_ENABLE��� PROTECT_LITE.<CAL_R_EXPECTEDPROTECT_LITE_R_CALIB_0_R_REF< CAL_R_DELTA"PROTECT_LITE_R_CALIB_0_R_DELTA_MAX�LCHIRP_CUR_FREQhPROTECT_LITE_DIAGNOSTICS_STRUCT_0_CALIBRATION_AND_DIAGNOSTICS_RX_CMPST_0_LINEARCHIRP_0_CURRENT_FREQUENCY| LCHIRP_FSTOP\PROTECT_LITE_DIAGNOSTICS_STRUCT_0_CALIBRATION_AND_DIAGNOSTICS_RX_CMPST_0_LINEARCHIRP_0_FSTOP| LCHIRP_AMP`PROTECT_LITE_DIAGNOSTICS_STRUCT_0_CALIBRATION_AND_DIAGNOSTICS_RX_CMPST_0_LINEARCHIRP_0_AMPLITUDECTCALI_TUNE_APP_EN2PROTECT_LITE_SMART_CALIBRATION_APPROVE_TUNE_ENABLEDT CALI_NORM_EN4PROTECT_LITE_SMART_CALIBRATION_NORMALIZE_REDC_ENABLEELCALI_TEMP_OFFSET*PROTECT_LITE_SMART_CALIBRATION_TEMP_OFFSETFTCALI_MIN_EST_TMP3PROTECT_LITE_SMART_CALIBRATION_MIN_EST_AMBIENT_TEMPGTCALI_MAX_EST_TMP3PROTECT_LITE_SMART_CALIBRATION_MAX_EST_AMBIENT_TEMPPPROTECT_LITE_EN2PROTECT_LITE_PROTECT_LITE_CTRL_PROTECT_LITE_ENABLEHCAL_EN1PROTECT_LITE_PROTECT_LITE_CTRL_CALIBRATION_ENABLEHDIAG_EN1PROTECT_LITE_PROTECT_LITE_CTRL_DIAGNOSTICS_ENABLEL CAL_CHECKSUM,PROTECT_LITE_VAR_ARRAY_CHECK_SUM_CALIBRATION�H CAL_STATUS/PROTECT_LITE_VAR_ARRAY_IMPEDANCE_MEASURE_STATUS�LCAL_R5PROTECT_LITE_VAR_ARRAY_MEASURED_IMPEDANCE_CALIBRATION�PCAL_SET_STATUS3PROTECT_LITE_VAR_ARRAY_IMPEDANCE_THRESH_CALC_STATUSLCAL_R_SELECTED-PROTECT_LITE_VAR_ARRAY_INITIAL_CALI_IMPEDANCE LTEMP_COIL_RATE/PROTECT_LITE_VAR_ARRAY_RATE_OF_COIL_TEMP_CHANGE� H TEMP_EST_COR)PROTECT_LITE_VAR_ARRAY_TEMP_EST_CORRECTED� H TEMP_COIL_C.PROTECT_LITE_VAR_ARRAY_TEMP_MEASURED_CORRECTED�LFIX_MOD_MAX_EXC.PROTECT_LITE_VAR_ARRAY_FIX_MODEL_MAX_EXCURSION�L DD_MAX_EXC0PROTECT_LITE_VAR_ARRAY_DIRECT_DISP_MAX_EXCURSION�POVERS_REACT_GAIN.PROTECT_LITE_VAR_ARRAY_OVERSIGHT_REACTION_GAIN�< TONE_FLAG PROTECT_LITE_VAR_ARRAY_TONE_FLAG�PMAX_EXC_BEFO_LIM/PROTECT_LITE_VAR_ARRAY_MAX_EXCUR_BEFORE_LIMITER�T EXC_AFTER_LIM4PROTECT_LITE_VAR_ARRAY_MAX_EXCUR_VALUE_AFTER_LIMITER�DEXCUR_GAIN_MAX%PROTECT_LITE_VAR_ARRAY_EXCUR_GAIN_MAX�XTHERM_OVER_ACT_I4PROTECT_LITE_VAR_ARRAY_THERM_OVERRIDE_ACTIVATION_IND�PTHERM_R_ATT_MIN3PROTECT_LITE_VAR_ARRAY_THERMAL_RATE_ATTENUATION_MIN�LTHERM_ATTEN_MIN.PROTECT_LITE_VAR_ARRAY_THERMAL_ATTENUATION_MIN�TCB_THERM_ATT_MIN3PROTECT_LITE_VAR_ARRAY_COMB_THERMAL_ATTENUATION_MIN�LEXC_GAIN_DIG2MM,PROTECT_LITE_VAR_ARRAY_EXCURSION_GAIN_DIG2MM�H EXC_OFFSET_MM*PROTECT_LITE_VAR_ARRAY_EXCURSION_OFFSET_MM�(D TEMP_COIL_EST$PROTECT_LITE_VAR_ARRAY_TEMP_COIL_ESTBT CAL_AMBIENT9PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_CAL_AMBIENT_TEMPERATURE�CDDIAG_F0,PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_Z_CURVE_F0DXDIAG_F0_STATUS9PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_Z_CURVE_ANALYSIS_STATUSFdCAL_IMP_MEAS_CAL@PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_MEASURED_IMPEDANCE_CALIBRATIONGD CAL_R_OUT+PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_CAL_R_OUTKTDIAG_Z_LOW_DIFF6PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_DIAGNOSTICS_LOW_DIFFLLCAL_RE_EST_GAIN-PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_RE_EST_GAINMP CAL_ALPHA_REF1PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_ALPHA_REFERENCENH CAL_TC0_CALIB+PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_TC0_CALIBVPCAL_ZCURVE_F_LOW/PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_Z_CURVE_F_LOWY\CALI_EST_AMB_TMP9PROTECT_LITE_SMART_CALIB_VAR_ARRAY_ESTIMATED_AMBIENT_TEMP�8� PEQ20_1LPEQ20_1_ENABLE,PEQ20_1_PEQ20_PEQ20_CTRL_STRUCT_PEQ20_ENABLE�HPEQ20_1_FILTERS)PEQ20_1_PEQ20_PEQ20_FILTERBANK_PEQ20_BAND��9� PEQ20_2LPEQ20_2_ENABLE,PEQ20_2_PEQ20_PEQ20_CTRL_STRUCT_PEQ20_ENABLE�HPEQ20_2_FILTERS)PEQ20_2_PEQ20_PEQ20_FILTERBANK_PEQ20_BAND��L� MBDRC/TM_DRC1_LD_OP_LVL0MBDRC_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL�O@ M_DRC1_OP_LVL#MBDRC_DRC_1_STRUCT_DRC_OUTPUT_LEVEL�TTM_DRC2_LD_OP_LVL0MBDRC_DRC_2_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL�t@ M_DRC2_OP_LVL#MBDRC_DRC_2_STRUCT_DRC_OUTPUT_LEVEL�yTM_DRC3_LD_OP_LVL0MBDRC_DRC_3_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL��@ M_DRC3_OP_LVL#MBDRC_DRC_3_STRUCT_DRC_OUTPUT_LEVEL��D MBDRC_ENABLE$MBDRC_MBDRC_CTRL_STRUCT_MBDRC_ENABLE��� INPUT_CONDITIONERTIC_EN?INPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_ENABLE�\ IC_CH_BALAINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_CHAN_BAL�d IC_CH_BALSMHINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_CHAN_BAL_SMOOTH�h IC_MM_XO_ENMINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_MONOMIX_XOVER_ENABLE�d IC_H_XO_ENJINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_HALF_XOVER_ENABLE�/hIC_PPU_H_XO_BALKINPUT_CONDITIONER_INPUT_CONDITIONER_PPU_CTRL_STRUCT_INP_COND_HALF_XOVER_BAL��\� ACTISONIC�<ACTISONIC_ENABLEACTISONIC_ACTISONIC_ENABLE��� LIMITERTLI_DRC_LD_OP_LVL2LIMITER_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL�!D LI_DRC_OP_LVL%LIMITER_DRC_1_STRUCT_DRC_OUTPUT_LEVEL�&D LI_ENABLE*LIMITER_LIMITER_CTRL_STRUCT_LIMITER_ENABLE��0� INPUT_ENHANCE\IE_DRC_LD_OP_LVL8INPUT_ENHANCE_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL�&H IE_DRC_OP_LVL+INPUT_ENHANCE_DRC_1_STRUCT_DRC_OUTPUT_LEVEL�+X IE_ENABLE8TG23_TONE_DIVIDESDCA_TG23_TONE_DIVIDER^@XU22_FDL_MES_OFFSDCA_XU22_FDL_MESSAGE_OFFSET�`@XU22_FDL_MES_LENSDCA_XU22_FDL_MESSAGE_LENGTH��)� WRITE_DETECT�#� EVENT_LOGGER< EVLOG_HEADEREVENT_LOGGER_EVENT_LOG_HEADER�0EVLOG_ENEVENT_LOGGER_ENABLED�8 BUFFER_STATUSEVENT_LOGGER_BUFFER_STATUS�@ EVLOG_ST_OFF EVENT_LOGGER_START_STREAM_OFFSET� 8 WAS_DISABLEDEVENT_LOGGER_WAS_DISABLED� <EVLOG_TS_SHIFTEVENT_LOGGER_TIMESTAMP_SHIFT��X*� ASP_MIXER8ASP_MIX_ENABLEASP_MIXER_ASP_MIX_ENABLE��\B SHORT_DETECT8SHORT_DETECTEDSHORT_DETECT_SHORT_DETECTED���3� VMON_SYNTHESIS,ENABLEVMON_SYNTHESIS_ENABLE�PVMS_AC_MOD_IMAX3VMON_SYNTHESIS_ANALOG_CLIPPING_MODULATION_INDEX_MAX�P VMS_AC_INT_R0VMON_SYNTHESIS_ANALOG_CLIPPING_INTERNAL_RESISTOR�P VMS_AC_EXT_R0VMON_SYNTHESIS_ANALOG_CLIPPING_EXTERNAL_RESISTOR�L VMS_AC_LOAD_R,VMON_SYNTHESIS_ANALOG_CLIPPING_LOAD_RESISTOR�LVMS_IMC_CAL_ST.VMON_SYNTHESIS_IMON_CALIBRATION_IMON_CAL_STATE�PVMS_IMC_CAL_LN2VMON_SYNTHESIS_IMON_CALIBRATION_CALIBRATION_LENGTH�PVMS_IMC_COR_MAX3VMON_SYNTHESIS_IMON_CALIBRATION_IMON_CORRECTION_MAX�LVMS_IMC_APT_RATE*VMON_SYNTHESIS_IMON_CALIBRATION_ADAPT_RATE�`VMS_IMC_SINE_THR>VMON_SYNTHESIS_IMON_CALIBRATION_SINEGENERATORSENSE_0_THRESHOLD�PVMS_IMC_IMON_COR/VMON_SYNTHESIS_IMON_CALIBRATION_IMON_CORRECTION�8 VMON_SCALINGVMON_SYNTHESIS_VMON_SCALING�8 IMON_SCALINGVMON_SYNTHESIS_IMON_SCALING�@ERROR_VOL_ATTACKVMON_SYNTHESIS_ERROR_VOL_ATTACK�@VMS_ERR_VOL_RLS VMON_SYNTHESIS_ERROR_VOL_RELEASE��4� BOOT_BEEP<BOOT_BEEP_ENABLEBOOT_BEEP_BOOT_BEEP_ENABLE�4 DSP_BEEP_FREQBOOT_BEEP_DSP_BEEP_FREQ�8DSP_BEEP_LEVELBOOT_BEEP_DSP_BEEP_LEVEL�8BB_DSP_BEEP_DURBOOT_BEEP_DSP_BEEP_DURATION�8GPIO_BEEP_FREQBOOT_BEEP_GPIO_BEEP_FREQ�8GPIO_BEEP_LEVELBOOT_BEEP_GPIO_BEEP_LEVEL�4 BEEP_PENDINGBOOT_BEEP_BEEP_PENDING��1� TWEETER_XOVER�80� TWEETER_LIMITER\TLI_DRC_LD_OP_LV:TWEETER_LIMITER_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL�!LTLI_DRC_OP_LVL-TWEETER_LIMITER_DRC_1_STRUCT_DRC_OUTPUT_LEVEL�&\ TLI_ENABLEBTWEETER_LIMITER_TWEETER_LIMITER_CTRL_STRUCT_TWEETER_LIMITER_ENABLE��5� TWEETER_ENHANCE�<7� SWDEH(SWDE_ENSWDE_SWDE_ENABLE, SWDE_SW_ENSWDE_SWDE_SW_ENABLE, SWDE_DE_ENSWDE_SWDE_DE_ENABLE8SWDE_SW_M_F1_B0SWDE_ST_WIDE_MID_FILT_1_B08SWDE_SW_M_F1_B1SWDE_ST_WIDE_MID_FILT_1_B18SWDE_SW_M_F1_B2SWDE_ST_WIDE_MID_FILT_1_B2<SWDE_SW_M_F1_MA1SWDE_ST_WIDE_MID_FILT_1_MA1<SWDE_SW_M_F1_MA2SWDE_ST_WIDE_MID_FILT_1_MA28SWDE_SW_M_F2_B0SWDE_ST_WIDE_MID_FILT_2_B0 8SWDE_SW_M_F2_B1SWDE_ST_WIDE_MID_FILT_2_B1 8SWDE_SW_M_F2_B2SWDE_ST_WIDE_MID_FILT_2_B2 <SWDE_SW_M_F2_MA1SWDE_ST_WIDE_MID_FILT_2_MA1 <SWDE_SW_M_F2_MA2SWDE_ST_WIDE_MID_FILT_2_MA2 8SWDE_SW_M_F3_B0SWDE_ST_WIDE_MID_FILT_3_B08SWDE_SW_M_F3_B1SWDE_ST_WIDE_MID_FILT_3_B18SWDE_SW_M_F3_B2SWDE_ST_WIDE_MID_FILT_3_B2<SWDE_SW_M_F3_MA1SWDE_ST_WIDE_MID_FILT_3_MA1<SWDE_SW_M_F3_MA2SWDE_ST_WIDE_MID_FILT_3_MA28SWDE_SW_S_F1_B0SWDE_ST_WIDE_SIDE_FILT_1_B08SWDE_SW_S_F1_B1SWDE_ST_WIDE_SIDE_FILT_1_B18SWDE_SW_S_F1_B2SWDE_ST_WIDE_SIDE_FILT_1_B2@SWDE_SW_S_F1_MA1SWDE_ST_WIDE_SIDE_FILT_1_MA1@SWDE_SW_S_F1_MA2SWDE_ST_WIDE_SIDE_FILT_1_MA28SWDE_SW_S_F2_B0SWDE_ST_WIDE_SIDE_FILT_2_B08SWDE_SW_S_F2_B1SWDE_ST_WIDE_SIDE_FILT_2_B18SWDE_SW_S_F2_B2SWDE_ST_WIDE_SIDE_FILT_2_B2@SWDE_SW_S_F2_MA1SWDE_ST_WIDE_SIDE_FILT_2_MA1@SWDE_SW_S_F2_MA2SWDE_ST_WIDE_SIDE_FILT_2_MA28SWDE_SW_S_F3_B0SWDE_ST_WIDE_SIDE_FILT_3_B08SWDE_SW_S_F3_B1SWDE_ST_WIDE_SIDE_FILT_3_B18SWDE_SW_S_F3_B2SWDE_ST_WIDE_SIDE_FILT_3_B2@SWDE_SW_S_F3_MA1SWDE_ST_WIDE_SIDE_FILT_3_MA1 @SWDE_SW_S_F3_MA2SWDE_ST_WIDE_SIDE_FILT_3_MA2!4SWDE_SW_M_SCALESWDE_ST_WIDE_MID_SCALE"4SWDE_SW_M_SHIFTSWDE_ST_WIDE_MID_SHIFT#4SWDE_SW_S_SCALESWDE_ST_WIDE_SIDE_SCALE$4SWDE_SW_S_SHIFTSWDE_ST_WIDE_SIDE_SHIFT%8SWDE_DE_M_F1_B0SWDE_D_ENH_MID_FILT_1_B0&8SWDE_DE_M_F1_B1SWDE_D_ENH_MID_FILT_1_B1'8SWDE_DE_M_F1_B2SWDE_D_ENH_MID_FILT_1_B2(<SWDE_DE_M_F1_MA1SWDE_D_ENH_MID_FILT_1_MA1)<SWDE_DE_M_F1_MA2SWDE_D_ENH_MID_FILT_1_MA2*8SWDE_DE_M_F2_B0SWDE_D_ENH_MID_FILT_2_B0+8SWDE_DE_M_F2_B1SWDE_D_ENH_MID_FILT_2_B1,8SWDE_DE_M_F2_B2SWDE_D_ENH_MID_FILT_2_B2-<SWDE_DE_M_F2_MA1SWDE_D_ENH_MID_FILT_2_MA1.<SWDE_DE_M_F2_MA2SWDE_D_ENH_MID_FILT_2_MA2/8SWDE_DE_M_F3_B0SWDE_D_ENH_MID_FILT_3_B008SWDE_DE_M_F3_B1SWDE_D_ENH_MID_FILT_3_B118SWDE_DE_M_F3_B2SWDE_D_ENH_MID_FILT_3_B22<SWDE_DE_M_F3_MA1SWDE_D_ENH_MID_FILT_3_MA13<SWDE_DE_M_F3_MA2SWDE_D_ENH_MID_FILT_3_MA248SWDE_DE_S_F1_B0SWDE_D_ENH_SIDE_FILT_1_B058SWDE_DE_S_F1_B1SWDE_D_ENH_SIDE_FILT_1_B168SWDE_DE_S_F1_B2SWDE_D_ENH_SIDE_FILT_1_B27<SWDE_DE_S_F1_MA1SWDE_D_ENH_SIDE_FILT_1_MA18<SWDE_DE_S_F1_MA2SWDE_D_ENH_SIDE_FILT_1_MA298SWDE_DE_S_F2_B0SWDE_D_ENH_SIDE_FILT_2_B0:8SWDE_DE_S_F2_B1SWDE_D_ENH_SIDE_FILT_2_B1;8SWDE_DE_S_F2_B2SWDE_D_ENH_SIDE_FILT_2_B2<<SWDE_DE_S_F2_MA1SWDE_D_ENH_SIDE_FILT_2_MA1=<SWDE_DE_S_F2_MA2SWDE_D_ENH_SIDE_FILT_2_MA2>8SWDE_DE_S_F3_B0SWDE_D_ENH_SIDE_FILT_3_B0?8SWDE_DE_S_F3_B1SWDE_D_ENH_SIDE_FILT_3_B1@8SWDE_DE_S_F3_B2SWDE_D_ENH_SIDE_FILT_3_B2A<SWDE_DE_S_v3_MA1SWDE_D_ENH_SIDE_FILT_3_MA1B<SWDE_DE_S_F3_MA2SWDE_D_ENH_SIDE_FILT_3_MA2C4SWDE_DE_M_SCALESWDE_D_ENH_MID_SCALED4SWDE_DE_M_SHIFTSWDE_D_ENH_MID_SHIFTE4SWDE_DE_S_SCALESWDE_D_ENH_SIDE_SCALEF4SWDE_DE_S_SHIFTSWDE_D_ENH_SIDE_SHIFTI0SWDE_XFADE_BALSWDE_SWDE_BALANCE�/� SHARED_PATCHING_STRUCTUREPSPTCH_MD_SLW_FRM-SHARED_PATCHING_STRUCTURE_MBDRC_SLEW_N_FRAMES